JAJSSL4A December 2023 – September 2024 LMX1214
PRODUCTION DATA
When the device is powered up, the power-on reset (POR) resets all registers to a default state as well as resets all state machines and dividers. For the power-on reset state, all the dividers are bypassed and the device performs as a 4-output buffer. Wait 100 µs after the power supply rails before programming other registers to verify that this reset is finished. When there is no input clock present, the device power-on reset happens properly and functions well, but the device draws less current. The current changes after an input clock is added.
Performing a software power-on reset by writing RESET = 1 in the SPI bus is also possible and generally good practice. The RESET bit self-clears when the user writes to another register. The SPI bus can be used to override these states to the desired settings.
Although the device does have an automatic power-on reset, the device can be impacted by different ramp rates on the different supply pins, especially in the presence of a strong input clock signal. TI therefore recommends to do a software reset after POR. This can be done by programming RESET = 1. The reset bit can be cleared by programming any other register or setting RESET back to 0. Even at the maximum allowed SPI bus speed, the software reset event always completes before the subsequent SPI write.