JAJSSL4A December   2023  – September 2024 LMX1214

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power-On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
      4. 6.3.4 AUXCLK Output
        1. 6.3.4.1 AUXCLKOUT Output Format
        2. 6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers
      5. 6.3.5 SYNC Input Pins
        1. 6.3.5.1 SYNC Pins Common-Mode Voltage
        2. 6.3.5.2 Windowing Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYNC Input Configuration
      2. 8.1.2 Treatment of Unused Pins
      3. 8.1.3 Current Consumption
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

2.4 V ≤ VCC ≤ 2.6 V, –40°C ≤ TA ≤ +85°C. Typical values are at VCC = 2.5 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption
ICC Supply current (1) Powered up, all outputs on 530 mA
Powered up, all outputs off 290
Powered down 12
IADD Additive output current OUTx_PWR = 7 70 mA
Divider current Divide, CLK_DIV = 8 36
Isync Supply current with SYNC enable 685 mA
SYNC Pins
VSYNC_single Voltage input range DC Coupled single ended 0.6 1 Vpp
VSYNC Voltage input range AC differential voltage 0.8 2 Vpp
VCM Input common mode Differential 100 Ω Termination, DC coupled
Set externally		 1.2 1.3 2 V
Clock Input
fIN Input frequency Buffer Mode Only 0.3 18(2) GHz
PIN Input power Single-ended power at CLKIN_P or CLKIN_N 0 10 dBm
Clock Outputs
fOUT Output frequency Divide-by-2 Without Sync (pin mode) 0.15 8 GHz
fOUT Output frequency Divide-by-2 With Sync 0.15 6.4 GHz
fOUT Output frequency Buffer Mode 0.3 18(2)
fOUT Output frequency AUXCLK output 1 800 MHz
pOUT Output power Single-Ended fCLKLOUT= 6 GHz
OUTx_PWR = 7		 6.5 dBm
fCLKLOUT= 12.8 GHz
OUTx_PWR = 7 		3.5
fCLKLOUT= 18 GHz
OUTx_PWR = 7		 1.5
Φimb Output phase imbalance between P & N Buffer mode 5 ps
tRISE Rise time (20% to 80%) fCLKOUT = 300 MHz 45 ps
tFALL Fall time (20% to 80%) fCLKOUT = 300 MHz 45 ps
tMUTE Output mute time Falling edge of OE pin 30 µs
tUNMUTE Output unmute time Rising edge of OE pin 30 µs
Propagation Delay and Skew
| tSKEW | Magnitude of skew between outputs CLKOUTx to CLKOUTy, not AUXCLK 1 10 ps
tDLY Propagation delay TA=25oC Bypass Mode 120 ps
Divide Mode 125
ΔtDLY/ΔT Propagation delay variation over temperature Bypass Mode 0.06 ps/C
Noise, Jitter, and Spurs
JCKx Additive jitter Additive Jitter. 12k to 100 MHz integration bandwidth. Buffer Mode 5 fs, rms
Flicker 1/f flicker noise Slew Rate > 8 V/ns, fCLK=6 GHz Buffer Mode –154 dBc/Hz
NFL Noise Floor fOUT = 6 GHz; fOffset = 100 MHz Buffer Mode –161 dBc/Hz
NFL Divide-by-2 –160.5
H2 Second harmonic fOUT = 6 GHz (differential), Buffer Mode –25 dBc
fOUT = 6 GHz (single-ended), Buffer Mode –12
fOUT = 6 GHz, single-ended, Divide by 2 –13.5
Coupling AUXCLK to CLKOUT coupling fout = 6 GHz, Single-ended; fAUXCLK = 300MHz –70 dBc
NFL Noise Floor fAUXCLK = 300MHz; LVDS mode –152 dBc
NFL Noise Floor fAUXCLK = 300MHz; CML mode –151 dBc
P leakage Leakage power Input to Output Chip power down Single Ended Input –45 dBc
P leakage Leakage power Input to Output Pin OE = 0 Single Ended Input –40 dBc
Digital Interface (SCK, SDI, CS#, MUXOUT,CLKx_EN,MUXSEL,DIVSELx)
VIH High-level input voltage SCK, SDI, CS# 1.4 3.3 V
High-level input voltage CLKx_EN,DIVSELx,MUXSEL 1.4 3.3 V
VIL Low-level input voltage SCK, SDI, CS# 0 0.4 V
Low-level input voltage CLKx_EN,DIVSELx,MUXSEL 0 0.4 V
IIH High-level input current SCK, SDI, CS# –42 42 µA
High-level input current CLKx_EN,DIVSELx,MUXSEL –42 42 µA
IIL Low-level input current SCK, SDI, CS# –25 25 µA
Low-level input current CLKx_EN,DIVSELx,MUXSEL –25 25 µA
VOH High-level output voltage MUXOUT IOH = 5 mA 1.4 Vcc V
High-level output voltage IOH = 0.1 mA 2.2 Vcc V
VOL Low-level output voltage MUXOUT IOL = 5 mA 0.45 V
(1) Unless Otherwise Stated, fCLKIN=6 GHz, CLK_MUX=Buffer, All clocks on with OUTx_PWR=7.
(2) SYNC and dividers supported up to 12.8GHz frequency