JAJSV88 June   2024 LMX1860-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ Pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Generation (Retime)
            3. 6.3.6.3.2.3 Other Guidance For SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plot
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power-Up Timing
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1.2 Treatment of Unused Pins

In many cases, not all pins are used. Table 7-1 lists the recommendation on how to handle these unused pins.

Table 7-1 Treatment of Unused or Partially Used Pins
PIN(S) TREATMENT
All VCC Pins These pins must always be connected to the power supply. If the block that powers by these VCC pins (as implied by the pin name) is not used, then the bypassing can be minimized or eliminated.
SYSREFREQ
  1. If driving single-ended input, the complementary input pin terminates based on Section 7.1.1.
  2. If the SYSREFREQ pins are unused, tie the pins to the VCC with a 1kΩ resistor.
CLKIN Complementary Input If driving single-ended input, the complementary pin terminate with 50Ω resistor AC-coupled to ground.
VBIAS01 and VBIAS23 If multiplier is not used, connect these pins capacitor (1µF) to ground.
CLKOUT

SYSREFOUT

LOGICLKOUT

LOGISYSREFOUT

 If not used, connect a AC-coupling capacitor and 50Ω to ground.
CE, CLKx_EN, LOGIC_EN, SYSREF_EN
  1. If operating device in SPI controlled mode, these pins must tied to VCC with 1kΩ resistor.
  2. If not operating in both SPI and pin mode, these pins must connect to ground with 1kΩ resistor.
CAL, MUXSELx, DIVSELx, PWRSELx
  1. If these pins are unused, connect these pins to ground with a 1kΩ resistor.