JAJSV88 June   2024 LMX1860-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ Pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Generation (Retime)
            3. 6.3.6.3.2.3 Other Guidance For SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plot
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power-Up Timing
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions



Figure 4-1 PAP0064E Package64-Pin HTQFPTop View
Table 4-1 Pin Functions
NO. NAME TYPE(1) DESCRIPTION
1 MUXOUT O Multiplexed pin serial data readback (SDO) and lock status of the multiplier.
2 CE I Chip Enable
3 SYSREFREQ_P I Differential SYSREF request input for JESD204B/C support. Internal 50Ω AC coupled to internal common-mode voltage or capacitor to GND. Supports AC and DC coupling which can directly accept a common mode voltage of 1.2V to 2V.
4 SYSREFREQ_N I Differential SYSREF request input for JESD204B/C support. Internal 50Ω AC coupled to internal common-mode voltage or capacitor to GND. Supports AC and DC coupling which can directly accept a common mode voltage of 1.2V to 2V.
5 VCC_CLKIN PWR Connect to a 2.5V supply. Recommend a shunt RF wideband capacitor (typically 0.1µF or smaller) close to the pin in parallel with larger capacitors (typically 1µF and 10µF). Large capacitors can be placed further away from the pin.
6 GND GND Ground these pins.
7 CLKIN_P I Differential reference input clock. Internal 50Ω termination. AC-couple with a capacitor appropriate to the input frequency (typically 0.1µF or smaller). If using single-ended, terminate unused pin with 50Ω resistor AC-coupled to ground.
8 CLKIN_N
9 GND GND Ground these pins.
10 PWRSEL0 I Selects output power level in pin mode.
11 PWRSEL1 I Selects output power level in pin mode.
12 PWRSEL2 I Selects output power level in pin mode.
13 NC NC No connect pin (Connect to ground with 1kΩ resistor.)
14 SCK I SPI clock. High impedance CMOS input. Accepts up to 3.3V.
15 SDI I SPI data input. High impedance CMOS input. Accepts up to 3.3V.
16 CS# I SPI chip select. High impedance CMOS input. Accepts up to 3.3V.
17 CAL I Calibration pin used in multiplier mode.
18 SYSREFOUT0_N O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
19 SYSREFOUT0_P O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
20 VCC01 PWR Connect to a 2.5V supply. Recommend a shunt RF wideband capacitor (typically 0.1µF or smaller) close to the pin in parallel with larger capacitors (typically 1µF and 10µF). Large capacitors can be placed bit further away from the pin.
21 GND GND Ground these pins.
22 CLKOUT0_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
23 CLKOUT0_P O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
24 GND GND Ground these pins.
25 CLK0_EN I Enable / Disable the individual output channel.
26 CLK1_EN I Enable / Disable the individual output channel.
27 VCC01 PWR Connect to a 2.5V supply. Recommend a shunt RF wideband capacitor (typically 0.1µF or smaller) close to the pin in parallel with larger capacitors (typically 1µF and 10µF). Large capacitors can be placed bit further away from the pin.
28 GND GND Ground these pins.
29 CLKOUT1_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
30 CLKOUT1_P O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
31 GND GND Ground these pins.
32 VBIAS01 BYP Bypass this pin to GND with a 10nF capacitor for optimal noise performance in multiplier mode.
33 SYSREFOUT1_N O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
34 SYSREFOUT1_P O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
35 DIVSEL2 I Select the divider value or multiplier value in divider or multiplier mode in pin configuration.
36 DIVSEL1 I Select the divider value or multiplier value in divider or multiplier mode in pin configuration.
37 DIVSEL0 I Select the divider value or multiplier value in divider or multiplier mode in pin configuration.
38 LOGISYSREFOUT_N O Differential clock output pair. Selectable CML, or LVDS format. Programmable common-mode voltage.
39 LOGISYSREFOUT_P O Differential clock output pair. Selectable CML, or LVDS format. Programmable common-mode voltage.
40 VCC_LOGICLK PWR Connect to a 2.5V supply. Recommend a shunt RF wideband capacitor (typically 0.1µF or smaller) close to the pin in parallel with larger capacitors (typically 1µF and 10µF). Large capacitors can be placed bit further away from the pin.
41 GND GND Ground these pins.
42 LOGICLKOUT_N O Differential clock output pair. Selectable CML, or LVDS format. Programmable common-mode voltage.
43 LOGICLKOUT_P O Differential clock output pair. Selectable CML, or LVDS format. Programmable common-mode voltage.
44 LOGIC_EN I Enable / disable the logic channel in pin mode.
45 MUXSEL1 I Select the operating mode buffer, divider or multiplier in pin mode configuration.
46 MUXSEL0 I Select the operating mode buffer, divider or multiplier in pin mode configuration.
47 SYSREFOUT2_N O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
48 SYSREFOUT2_P O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
49

VBIAS23

 BYP Bypass this pin to GND with a 10µF and 0.1µF capacitor for optimal noise performance in multiplier mode.
50 GND GND Ground these pins.
51 CLKOUT2_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
52 CLKOUT2_P O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
53 GND GND Ground these pins.
54 VCC23 PWR Connect to a 2.5V supply. Recommend a shunt RF wideband capacitor (typically 0.1µF or smaller) close to the pin in parallel with larger capacitors (typically 1µF and 10µF). Large capacitors can be placed bit further away from the pin.
55 CLK2_EN I Enable / Disable the individual output channel.
56 CLK3_EN I Enable / Disable the individual output channel.
57 GND GND Ground these pins.
58 CLKOUT3_N O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
59 CLKOUT3_P O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50Ω resistor with programmable output swing. AC coupling required.
60 GND GND Ground these pins.
61 VCC23 PWR Connect to a 2.5V supply. Recommend a shunt RF wideband capacitor (typically 0.1µF or smaller) close to the pin in parallel with larger capacitors (typically 1µF and 10µF). Large capacitors can be placed bit further away from the pin.
62 SYSREFOUT3_N O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
63 SYSREFOUT3_P O Differential SYSREF CML output pairs for JESD204B/C support. Supports AC and DC coupling with programmable common-mode voltage of 0.6V to 2V.
64 SYSREF_EN I Enable / disable the SYSREF section in pin mode configuration.
DAP DAP GND Ground the pad.
(1) I = Input, O = Output, GND = Ground, PWR = Power, BYP = Bypass