SNAS851 December   2023 LMX1906-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
            3. 6.3.6.3.2.3 Other Pointers With SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plots
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Timing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.1 Device Registers

Table 7-4 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 7-4 should be considered as reserved locations and the register contents should not be modified.

Table 7-4 DEVICE Registers
OffsetAcronymRegister NameSection
0hR0Section 7.5.1.1
2hR2Section 7.5.1.2
3hR3Section 7.5.1.3
4hR4Section 7.5.1.4
5hR5Section 7.5.1.5
6hR6Section 7.5.1.6
7hR7Section 7.5.1.7
8hR8Section 7.5.1.8
9hR9Section 7.5.1.9
BhR11Section 7.5.1.10
ChR12Section 7.5.1.11
DhR13Section 7.5.1.12
EhR14Section 7.5.1.13
FhR15Section 7.5.1.14
10hR16Section 7.5.1.15
11hR17Section 7.5.1.16
12hR18Section 7.5.1.17
13hR19Section 7.5.1.18
14hR20Section 7.5.1.19
15hR21Section 7.5.1.20
16hR22Section 7.5.1.21
17hR23Section 7.5.1.22
18hR24Section 7.5.1.23
19hR25Section 7.5.1.24
1ChR28Section 7.5.1.25
1DhR29Section 7.5.1.26
21hR33Section 7.5.1.27
22hR34Section 7.5.1.28
41hR65Section 7.5.1.29
43hR67Section 7.5.1.30
48hR72Section 7.5.1.31
49hR73Section 7.5.1.32
4BhR75Section 7.5.1.33
4ChR76Section 7.5.1.34
56hR86Section 7.5.1.35
5AhR90Section 7.5.1.36

Complex bit access types are encoded to fit into small table cells. Table 7-5 shows the codes that are used for access types in this section.

Table 7-5 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.5.1.1 R0 Register (Offset = 0h) [Reset = 0000h]

R0 is shown in Table 7-6.

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Table 7-6 R0 Register Field Descriptions
BitFieldTypeResetDescription
15-3UNDISCLOSEDR/W0h Program this field to 0x0.
2POWERDOWNR/W0h Sets the device in a low-power state. The states of other registers are maintained.
1UNDISCLOSEDR/W0h Program this field to 0x0.
0RESETR/W0h Soft Reset. Resets the entire logic and registers (equivalent to power-on reset). Self-clearing on next register write.

7.5.1.2 R2 Register (Offset = 2h) [Reset = 0223h]

R2 is shown in Table 7-7.

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Table 7-7 R2 Register Field Descriptions
BitFieldTypeResetDescription
15-11UNDISCLOSEDR0h Program this field to 0x0.
10UNDISCLOSEDR/W0h Program this field to 0x0.
9-6SMCLK_DIV_PRER/W8h Pre-divider for State Machine clock (one hot divider).The state machine clock is divided from the input clock. The output of the pre-divider should be ≤1600MHz. Values other than those listed are reserved.
2h = /2
4h = /4
8h = /8
5SMCLK_ENR/W1h Enables the state machine clock generator. Only required to calibrate the multiplier, and for multiplier lock detect (including on MUXOUT pin). If the multiplier is not used, or if the multiplier lock detect feature is not used, the state machine clock generator can be disabled to minimize crosstalk.
4-0UNDISCLOSEDR/W3h Program this field to 0x3.

7.5.1.3 R3 Register (Offset = 3h) [Reset = FF86h]

R3 is shown in Table 7-8.

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Table 7-8 R3 Register Field Descriptions
BitFieldTypeResetDescription
15CH3_ENR/W1h Enables CH3 (CLKOUT3, SYSOUT3). Setting this bit to 0 will completely disable CH3, overriding the state of other power-down/enable bits.
14CH2_ENR/W1h Enables CH2 (CLKOUT2, SYSOUT2). Setting this bit to 0 will completely disable CH2, overriding the state of other power-down/enable bits.
13CH1_ENR/W1h Enables CH1 (CLKOUT1, SYSOUT1). Setting this bit to 0 will completely disable CH1, overriding the state of other power-down/enable bits.
12CH0_ENR/W1h Enables CH0 (CLKOUT0, SYSOUT0). Setting this bit to 0 will completely disable CH0, overriding the state of other power-down/enable bits.
11LOGICLK_MUTE_CALR/W1h Mutes LOGIC outputs (LOGICLK/LOGISYS) during multiplier calibration.
10CH3_MUTE_CALR/W1h Mutes CH3 (CLKOUT3/SYSOUT3) during multiplier calibration.
9CH2_MUTE_CALR/W1h Mutes CH2 (CLKOUT2/SYSOUT2) during multiplier calibration.
8CH1_MUTE_CALR/W1h Mutes CH1 (CLKOUT1/SYSOUT1) during multiplier calibration.
7CH0_MUTE_CALR/W1h Mutes CH0 (CLKOUT0/SYSOUT0) during multiplier calibration.
6-3UNDISCLOSEDR0h Program this field to 0x0.
2-0SMCLK_DIVR/W6h Sets state machine clock divider. Further divides the output of the state machine clock pre-divider. Input frequency from SMCLK_DIV_PRE must be ≤ 1600 MHz. Output frequency must be ≤ 30 MHz. Divide value is 2SMCLK_DIV.
0h = /1
1h = /2
2h = /4
3h = /8
4h = /16
5h = /32
6h = /64
7h = /128

7.5.1.4 R4 Register (Offset = 4h) [Reset = 36FFh]

R4 is shown in Table 7-9.

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Table 7-9 R4 Register Field Descriptions
BitFieldTypeResetDescription
15-14UNDISCLOSEDR0h Program this field to 0x0.
13-11CLKOUT1_PWRR/W6h Sets the output power of CLKOUT1. Larger values correspond to higher output power.
10-8CLKOUT0_PWRR/W6h Sets the output power of CLKOUT0. Larger values correspond to higher output power.
7SYSREFOUT3_ENR/W1h Enables SYSREFOUT3 output buffer.
6SYSREFOUT2_ENR/W1h Enables SYSREFOUT2 output buffer.
5SYSREFOUT1_ENR/W1h Enables SYSREFOUT1 output buffer.
4SYSREFOUT0_ENR/W1h Enables SYSREFOUT0 output buffer.
3CLKOUT3_ENR/W1h Enables CLKOUT3 output buffer.
2CLKOUT2_ENR/W1h Enables CLKOUT2 output buffer.
1CLKOUT1_ENR/W1h Enables CLKOUT1 output buffer.
0CLKOUT0_ENR/W1h Enables CLKOUT0 output buffer.

7.5.1.5 R5 Register (Offset = 5h) [Reset = 4936h]

R5 is shown in Table 7-10.

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Table 7-10 R5 Register Field Descriptions
BitFieldTypeResetDescription
15UNDISCLOSEDR0h Program this field to 0x0.
14-12SYSREFOUT2_PWRR/W4h Sets the output power of SYSREFOUT2. Larger values correspond to higher output power. SYSREFOUT2_VCM must be set properly to bring the output common mode voltage within permissible limits.
11-9SYSREFOUT1_PWRR/W4h Sets the output power of SYSREFOUT1. Larger values correspond to higher output power. SYSREFOUT1_VCM must be set properly to bring the output common mode voltage within permissible limits.
8-6SYSREFOUT0_PWRR/W4h Sets the output power of SYSREFOUT0. Larger values correspond to higher output power. SYSREFOUT0_VCM must be set properly to bring the output common mode voltage within permissible limits.
5-3CLKOUT3_PWRR/W6h Sets the output power of CLKOUT3. Larger values correspond to higher output power.
2-0CLKOUT2_PWRR/W6h Sets the output power of CLKOUT2. Larger values correspond to higher output power.

7.5.1.6 R6 Register (Offset = 6h) [Reset = B6DCh]

R6 is shown in Table 7-11.

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Table 7-11 R6 Register Field Descriptions
BitFieldTypeResetDescription
15LOGICLKOUT_ENR/W1h Enables the logic clock output buffer.
14-12SYSREFOUT3_VCMR/W3h Sets the output common mode of SYSREFOUT3. SYSREFOUT3_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
11-9SYSREFOUT2_VCMR/W3h Sets the output common mode of SYSREFOUT2. SYSREFOUT2_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
8-6SYSREFOUT1_VCMR/W3h Sets the output common mode of SYSREFOUT1. SYSREFOUT1_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
5-3SYSREFOUT0_VCMR/W3h Sets the output common mode of SYSREFOUT0. SYSREFOUT0_PWR must be set properly to bring the minimum and maximum output voltage within permissible limits.
2-0SYSREFOUT3_PWRR/W4h Sets the output power of SYSREFOUT3. Larger values correspond to higher output power. SYSREFOUT3_VCM must be set properly to bring the output common mode voltage within permissible limits.

7.5.1.7 R7 Register (Offset = 7h) [Reset = 0001h]

R7 is shown in Table 7-12.

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Table 7-12 R7 Register Field Descriptions
BitFieldTypeResetDescription
15UNDISCLOSEDR0h Program this field to 0x0.
14-13LOGISYSREFOUT_VCMR/W0h In LVDS mode, sets the output common mode of the logic SYSREF output. Other output formats ignore this field.
0h = 1.2V
1h = 1.1V
2h = 1.0V
3h = 0.9V
12-11LOGICLKOUT_VCMR/W0h In LVDS mode, sets the output common mode of the logic clock output. Other output formats ignore this field.
0h = 1.2V
1h = 1.1V
2h = 1.0V
3h = 0.9V
10-9LOGISYSREF_DIV_PWR_PRER/W0h Sets the output power of the logic SYSREF pre-driver. Larger values correspond to higher output power.
8-7LOGICLK_DIV_PWR_PRER/W0h Sets the output power of the logic clock pre-driver. Larger values correspond to higher output power.
6-4LOGISYSREFOUT_PWRR/W0h Sets the output power of LOGISYSREFOUT for CML format only (other output formats ignore this field). Larger values correspond to higher output power.
3-1LOGICLKOUT_PWRR/W0h Sets the output power of LOGICLKOUT for CML format only (other output formats ignore this field). Larger values correspond to higher output power.
0LOGISYSREFOUT_ENR/W1h Enables the logic SYSREF output buffer.

7.5.1.8 R8 Register (Offset = 8h) [Reset = 0120h]

R8 is shown in Table 7-13.

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Table 7-13 R8 Register Field Descriptions
BitFieldTypeResetDescription
15-9UNDISCLOSEDR0h Program this field to 0x0.
8-6LOGICLK_DIV_PRER/W4h Sets pre-divider value for logic clock divider. Output of the pre-divider must be less than or equal to 3.2 GHz. When LOGICLK_DIV_PRE=1, it is also required register R79 is programmed to a value of 0x0005 and R90 to 0x0060 (LOGICLK_DIV_BYP2=1, LOGICLK_DIV_BYP3=1). Values for LOGICLK_DIV_PRE other than those listed below are reserved.
1h = /1
2h = /2
4h = /4
5LOGIC_ENR/W1h Enables LOGICLK subsystem (LOGICLKOUT, LOGISYSREFOUT). Setting this bit to 0x0 completely disables all LOGICLKOUT and LOGISYSREFOUT circuitry, overriding the state of other power-down/enable bits.
4UNDISCLOSEDR/W0h Program this field to 0x0.
3-2LOGISYSREFOUT_FMTR/W0h Selects the output driver format of the LOGISYSREFOUT output.
0h = LVDS
1h = Reserved
2h = CML
3h = Reserved
1-0LOGICLKOUT_FMTR/W0h Selects the output driver format of the LOGICLKOUT output.
0h = LVDS
1h = Reserved
2h = CML
3h = Reserved

7.5.1.9 R9 Register (Offset = 9h) [Reset = 0020h]

R9 is shown in Table 7-14.

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Table 7-14 R9 Register Field Descriptions
BitFieldTypeResetDescription
15-14SYSREFREQ_VCMR/W0h Sets the internal DC Bias for the SYSREFREQ pins. Bias must be enabled for AC-coupled inputs; but can be enabled and overdriven, or disabled, for DC-coupled inputs. SYSREFREQ DC pin voltage must be in the range of 0.7 V to VCC, including minimum and maximum signal swing.
0h = 1.3V
1h = 1.1V
2h = 1.5V
3h = Disabled
13SYNC_ENR/W0h Enables synchronization path for the dividers and allows the clock position capture circuitry to be enabled. Used for multi-device synchronization. Redundant if SYSREF_EN = 0x1.
12LOGICLK_DIV_PDR/W0h Disables the LOGICLK divider. LOGICLK pre-divider remains enabled. Used to reduce current consumption when bypassing the LOGICLK divider.
11LOGICLK_DIV_BYPR/W0h Bypasses the LOGICLK_DIV divider in order to derive the LOGICLK output directly from the LOGICLK_DIV_PRE divider. Should only be used when LOGICLK_DIV_PRE=1 as one of the steps to achieve a total divide of 1 for the LOGICLK. In order to achieve a divide by 1, the following steps are required.
1. Set LOGICLK_DIV_PRE=1
2. Ensure that register R79 is programmed to a value of 0x0005
3. Program R90 to 0x0060 (LOGICLK_DIV23=1, LOGICLK_DIV_DCC=1)
4. Set LOGICLK_DIV_BYP=1

When not wanting a total divide of 1 for the LOGICLK, this bit should be set to 0.
0h = Engage LOGICLK divider
1h = Bypass LOGICLK divider
10UNDISCLOSEDR/W0h Program this field to 0x0.
9-0LOGICLK_DIVR/W20h Sets LOGICLK divider value. Maximum input frequency from LOGICLK_DIV_PRE must be ≤ 3200 MHz. The maximum LOGICLKOUT frequency must be ≤ 800 MHz to avoid amplitude degradation.
0h = Reserved
1h = Reserved
2h = /2
3h = /3
3FFh = /1023

7.5.1.10 R11 Register (Offset = Bh) [Reset = 0000h]

R11 is shown in Table 7-15.

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Table 7-15 R11 Register Field Descriptions
BitFieldTypeResetDescription
15-0rb_CLKPOSR0h Stores a snapshot of the CLKIN signal rising edge positions relative to a SYSREFREQ rising edge, with the snapshot starting from the LSB and ending at the MSB. Each bit represents a sample of the CLKIN signal, separated by a delay determined by the SYSREFREQ_DLY_STEP field. The first and last bits of rb_CLKPOS are always set, indicating uncertainty at the capture window boundary conditions. CLKIN rising edges are represented by every sequence of two set bits from LSB to MSB, including bits at the boundary conditions. The position of the CLKIN rising edges in the snapshot, along with the CLKIN signal period and
the delay step size, can be used to compute the value of SYSREFREQ_DLY which maximizes setup and hold times for SYNC signals on the SYSREFREQ pins.

7.5.1.11 R12 Register (Offset = Ch) [Reset = 0000h]

R12 is shown in Table 7-16.

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Table 7-16 R12 Register Field Descriptions
BitFieldTypeResetDescription
15-0rb_CLKPOS[31:16]R0h MSB of rb_CLKPOS field.

7.5.1.12 R13 Register (Offset = Dh) [Reset = 0003h]

R13 is shown in Table 7-17.

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Table 7-17 R13 Register Field Descriptions
BitFieldTypeResetDescription
15-2UNDISCLOSEDR0h Program this field to 0x0.
1-0SYSREFREQ_DLY_STEPR/W3h Sets the step size of the delay element used in the SYSREFREQ path, both for SYSREFREQ input delay and for clock position captures. The recommended frequency range for each step size creates the maximum number of usable steps for a given CLKIN frequency. The ranges include some overlap to account for process and temperature variations. If the CLKIN frequency is covered by an overlapping span, larger delay step sizes improve the likelihood of detecting a CLKIN rising edge during a clock position capture. However, since larger values include more delay steps, larger step sizes have greater total delay variation across PVT relative to smaller step sizes.
0h = 28 ps (1.4GHz to 2.7GHz)
1h = 15 ps ( 2.4GHz to 4.7GHz)
2h = 11 ps (3.1GHz to 5.7GHz)
3h = 8 ps (4.5GHz to 12.8GHz)

7.5.1.13 R14 Register (Offset = Eh) [Reset = 0002h]

R14 is shown in Table 7-18.

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Table 7-18 R14 Register Field Descriptions
BitFieldTypeResetDescription
15-9UNDISCLOSEDR/W0h Program this field to 0x0.
8SYNC_MUTE_PDR/W0h Removes the mute condition on the SYSREFOUT and LOGISYSREFOUT pins during SYNC mode (SYSREFREQ_MODE = 0x0). Since the SYNC operation also resets the SYSREF dividers, the mute condition is usually desirable, and this bit can be left at the default value.
7-3UNDISCLOSEDR/W0h Program this field to 0x0.
2CLKPOS_CAPTURE_ENR/W0h Enables the windowing circuit which captures the clock position in
the rb_CLKPOS registers with respect to a SYSREF edge. The
windowing circuit must be cleared by toggling SYSREFREQ_CLR
high then low before a clock position capture. The first rising edge on the SYSREFREQ pins after clearing the windowing circuit
triggers the capture. The capture circuitry greatly increases supply current, and does not need to be enabled to delay the SYSREFREQ signal in SYNC or SYSREF modes. Once the desired value of SYSREFREQ_DLY is determined, set this bit to 0x0 to minimize current consumption. If SYNC_EN = 0 and SYSREF_EN = 0, the value of this bit is ignored, and the windowing circuit is disabled.
1SYSREFREQ_MODER/W1h Selects the function of the SYSREFREQ pins
0h = SYNC pin
1h = SYSREFREQ pin
0SYSREFREQ_LATCHR/W0h Latches the internal SYSREFREQ state to logic high on the first rising edge of the SYSREFREQ pins. This latch can be cleared by setting SYSREFREQ_CLR=1.

7.5.1.14 R15 Register (Offset = Fh) [Reset = 0B01h]

R15 is shown in Table 7-19.

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Table 7-19 R15 Register Field Descriptions
BitFieldTypeResetDescription
15-12UNDISCLOSEDR0h Program this field to 0x0.
11-10SYSREF_DIV_PRER/W2h Sets the SYSREF pre-divider. Maximum output frequency must be ≤ 3.2GHz.
0h = /1
1h = /2
2h = /4
3h = Reserved
9UNDISCLOSEDR/W1h Program this field to 0x1.
8SYSREF_ENR/W1h Enables SYSREF subsystem (and SYNC subsystem when SYSREFREQ_MODE = 0x0). Setting this bit to 0x0 completely disables all SYNC, SYSREF, and clock position capture circuitry, overriding the state of other power-down/enable bits except SYNC_EN. If SYNC_EN = 0x1, the SYNC path and clock position capture circuitry are still enabled, regardless of the state of SYSREF_EN.
7UNDISCLOSEDR/W0h Program this field to 0x0.
6-1SYSREFREQ_DLYR/W0h Sets the delay line step for the external SYSREFREQ signal. Each delay line step delays the SYSREFREQ signal by an amount equal to SYSREFREQ_DELAY_STEP x SYSREFREQ_DLY_STEP. In SYNC mode, the value for this field can be determined based on the rb_CLKPOS value to satisfy the internal setup and hold time of the SYNC signal with respect to the CLKIN signal. In SYSREF Repeater Mode, the value for this field can be used as a coarse global delay. Values greater than 0x3F are invalid. Since larger values include more delay steps, larger values have greater total step size variation across PVT relative to smaller values. Refer to the data sheet or the device TICS Pro profile for detailed description of the delay step computation procedure.
0SYSREFREQ_CLRR/W1h Clears SYSREFREQ_LATCH and resets synchronization path timing for SYSREFREQ signal. Holding this bit high keeps internal SYSREFREQ signal low in all modes except SYSREF repeater mode, overriding the state of SYSREFREQ_FORCE. This bit must be set and cleared once before the SYNC or clock position capture operations are performed.

7.5.1.15 R16 Register (Offset = 10h) [Reset = 1005h]

R16 is shown in Table 7-20.

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Table 7-20 R16 Register Field Descriptions
BitFieldTypeResetDescription
15-12SYSREF_PULSE_CNTR/W1h Programs the number of pulses generated in pulser mode. The pulser is a counter gating the SYSREF divider; consequently, the pulse duration and frequency are equal to the duty cycle and frequency of the SYSREF divider output, respectively.
0h = Reserved
1h = 1 pulse
2h = 2 pulses
Fh = 15 pulses
11-0SYSREF_DIVR/W5h Sets the SYSREF divider. Maximum input frequency from SYSREF_DIV_PRE must be ≤ 3200 MHz. Maximum output frequency must be ≤ 100 MHz. Odd divides (with duty cycle < 50%) are only allowed when the delay generators are bypassed.
0h = Reserved
1h = Reserved
2h = /2
3h = /3
FFFh = /4095

7.5.1.16 R17 Register (Offset = 11h) [Reset = 07F0h]

R17 is shown in Table 7-21.

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Table 7-21 R17 Register Field Descriptions
BitFieldTypeResetDescription
15-11UNDISCLOSEDR0h Program this field to 0x0.
10-4SYSREF0_DLY_IR/W7Fh Sets the delay step for the SYSREFOUT0 delay generator. Must satisfy SYSREFOUT0_DLY_I + SYSREFOUT0_DLY_Q = 127
3-2SYSREF0_DLY_PHASER/W0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT0 delay generator retimer.
0h = ICLK'
1h = QCLK'
2h = ICLK
3h = QCLK
1-0SYSREF_MODER/W0h Controls how the SYSREF signal is generated and is also impacted by the SYSREF_DLY_BYP field. Continuous mode generates a continuous SYSREF clock that is derived from the SYSREF divdier and delay. In pulser mode, a pulse at the SYSREFREQ pin causes a specific number (determined by SYSREF_PULSE_CNT) of pulses to be generated for the SYSREF outputs. In Repeater mode, a pulse at the SYSREFREQ pins will generate a single pulse at the SYSREF outputs and only the propagation delay through the device is added.
0h = Continuous
1h = Pulser
2h = Repeater
3h = Reserved

7.5.1.17 R18 Register (Offset = 12h) [Reset = FE00h]

R18 is shown in Table 7-22.

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Table 7-22 R18 Register Field Descriptions
BitFieldTypeResetDescription
15-9SYSREF1_DLY_IR/W7Fh Sets the delay step for the SYSREFOUT0 delay generator. Must satisfy SYSREFOUT0_DLY_I + SYSREFOUT0_DLY_Q = 127
8-7SYSREF1_DLY_PHASER/W0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT1 delay generator retimer.
0h = ICLK'
1h = QCLK'
2h = QCLK
3h = ICLK
6-0SYSREF0_DLY_QR/W0h Determines the strength of QCLK for delay generation. Must satisfy SYSREF0_DLY_I + SYSREF0_DLY_Q = 127

7.5.1.18 R19 Register (Offset = 13h) [Reset = FE00h]

R19 is shown in Table 7-23.

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Table 7-23 R19 Register Field Descriptions
BitFieldTypeResetDescription
15-9SYSREF2_DLY_IR/W7Fh Determines the strength of ICLK for delay generation. Must satisfy SYSREF2_DLY_I + SYSREF2_DLY_Q = 127
8-7SYSREF2_DLY_PHASER/W0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT2 delay generator retimer.
0h = ICLK'
1h = QCLK'
2h = QCLK
3h = ICLK
6-0SYSREF1_DLY_QR/W0h Determines the strength of QCLK for delay generation. Must satisfy SYSREF1_DLY_I + SYSREF1_DLY_Q = 127

7.5.1.19 R20 Register (Offset = 14h) [Reset = FE00h]

R20 is shown in Table 7-24.

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Table 7-24 R20 Register Field Descriptions
BitFieldTypeResetDescription
15-9SYSREF3_DLY_IR/W7Fh Sets the delay step for the SYSREFOUT1 delay generator. Must satisfy SYSREFOUT1_DLY_I + SYSREFOUT1_DLY_Q = 127
8-7SYSREF3_DLY_PHASER/W0h Sets the quadrature phase of the interpolator clock used for the SYSREFOUT3 delay generator retimer.
0h = ICLK'
1h = QCLK'
2h = QCLK
3h = ICLK
6-0SYSREF2_DLY_QR/W0h Determines the strength of QCLK for delay generation. Must satisfy SYSREF3_DLY_I + SYSREF3_DLY_Q = 127

7.5.1.20 R21 Register (Offset = 15h) [Reset = FE00h]

R21 is shown in Table 7-25.

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Table 7-25 R21 Register Field Descriptions
BitFieldTypeResetDescription
15-9LOGISYSREF_DLY_IR/W7Fh Determines the strength of logic ICLK for delay generation. Must satisfy LOGISYSREF_DLY_I+LOGISYSREF_DLY_Q = 127
8-7LOGISYSREF_DLY_PHASER/W0h Sets the quadrature phase of the interpolator clock used for the LOGISYSREFOUT delay generator retimer.
0h = ICLK'
1h = QCLK'
2h = QCLK
3h = ICLK
6-0SYSREF3_DLY_QR/W0h Determines the strength of QCLK for delay generation. Must satisfy SYSREFx_DLY_I + SYSREFx_DLY_Q = 127

7.5.1.21 R22 Register (Offset = 16h) [Reset = 0800h]

R22 is shown in Table 7-26.

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Table 7-26 R22 Register Field Descriptions
BitFieldTypeResetDescription
15-14SYSREF1_DLY_SCALER/W0h Sets the frequency range of the SYSREFOUT1 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz
1h = 200MHz to 400MHz
2h = 150MHz to 200MHz
3h = Reserved
13-12SYSREF0_DLY_SCALER/W0h Sets the frequency range of the SYSREFOUT0 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz
1h = 200MHz to 400MHz
2h = 150MHz to 200MHz
3h = Reserved
11-9SYSREF_DLY_DIVR/W4h Sets the delay generator clock division, determining the phase interpolator frequency and the delay generator resolution. Values other than those listed
below are reserved.
0h = /1 (Up to 1.6GHz)
1h = /2 (1.6GHz to 3.2GHz)
2h = /4 (3.2GHz to 6.4GHz)
4h = /8 (6.4GHz to 12.8GHz)
8-7UNDISCLOSEDR/W0h Program this field to 0x0.
6-0LOGISYSREF_DLY_QR/W0h Sets the delay step for the LOGISYSREFOUT delay generator. Must satisfy LOGISYSREFOUT_DLY_I + LOGISYSREFOUT_DLY_Q = 127.

7.5.1.22 R23 Register (Offset = 17h) [Reset = 4000h]

R23 is shown in Table 7-27.

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Table 7-27 R23 Register Field Descriptions
BitFieldTypeResetDescription
15TS_ENR/W0h Enables the on-die temperature sensor. Temperature sensor counter (TS_CNT_EN) must also be enabled for readback.
14UNDISCLOSEDR/W1h Program this field to 0x1.
13MUXOUT_ENR/W0h Enables or tri-states the MUXOUT pin driver.
0h = Tri-States
1h = Push-Pull
12-7UNDISCLOSEDR/W0h Program this field to 0x0.
6MUXOUT_SELR/W0h Selects MUXOUT pin function.
0h = Lock Detect
1h = Readback
5-4LOGISYSREF_DLY_SCALER/W0h Sets the frequency range of the LOGISYSREFOUT delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz
1h = 200MHz to 400MHz
2h = 150MHz to 200MHz
3h = Reserved
3-2SYSREF3_DLY_SCALER/W0h Sets the frequency range of the SYSREFOUT3 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz
1h = 200MHz to 400MHz
2h = 150MHz to 200MHz
3h = Reserved
1-0SYSREF2_DLY_SCALER/W0h Sets the frequency range of the SYSREFOUT2 delay generator. Set according to phase interpolator frequency.
0h = 400MHz to 800MHz
1h = 200MHz to 400MHz
2h = 150MHz to 200MHz
3h = Reserved

7.5.1.23 R24 Register (Offset = 18h) [Reset = 0000h]

R24 is shown in Table 7-28.

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Table 7-28 R24 Register Field Descriptions
BitFieldTypeResetDescription
15-14UNDISCLOSEDR0h Program this field to 0x0.
13-12UNDISCLOSEDR/W0h Program this field to 0x0.
11-1rb_TSR0h Readback value of on-die temperature sensor.
0TS_CNT_ENR/W0h Enables temperature sensor counter. Temperature sensor (EN_TS) must be enabled for accurate data.

7.5.1.24 R25 Register (Offset = 19h) [Reset = 0211h]

R25 is shown in Table 7-29.

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Table 7-29 R25 Register Field Descriptions
BitFieldTypeResetDescription
15-7UNDISCLOSEDR/W4h Program this field to 0x4.
6CLK_DIV_RSTR/W0h Resets the main clock divider. If the clock divider value is changed during operation, set this bit high then low after setting the new divider value. Synchronizing the device with the SYSREFREQ pins in SYSREFREQ_MODE = 0x0 and SYNC_EN = 0x1 also resets the main clock divider. This bit has no effect when outside of Divider Mode.
5-3CLK_DIVR/W2h CLK_DIV and CLK_MULT are aliases for the same field.
When CLK_MUX=1 (Buffer Mode), this field is ignored.
When CLK_MUX = 2 (Divider Mode), the clock divider is CLK_DIV + 1. Valid range for CLK_DIV is 1 to 7. Setting this to 0 disables the main clock divider and reverts to buffer mode.
When CLK_MUX = 3 (Multiplier Mode), CLK_MULT the multiplier value is CLK_MULT. Valid range is 1 to 4. Setting outside this range disables multiplier mode and reverts to buffer mode. Valid range is 0x1 to 0x4.
2-0CLK_MUXR/W1h Selects the function for the main clock outputs
0h = Reserved
1h = Buffer
2h = Dividers
3h = Multiplier

7.5.1.25 R28 Register (Offset = 1Ch) [Reset = 0A08h]

R28 is shown in Table 7-30.

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Table 7-30 R28 Register Field Descriptions
BitFieldTypeResetDescription
15-13UNDISCLOSEDR0h Program this field to 0x0.
12VCO_CORE_FORCER/W0h Forces the multiplier PLL's VCO to the value selected by VCO_CORE. Not required for Multiplier Mode programming, but can optionally be used to reduce calibration time.
11-9VCO_CORER/W5h When VCO_CORE_FORCE=0, specifies start VCO for multiplier calibration.
When VCO_CORE_FORCE=1, this VCO core is forced.
Programming of this field is not required for Multiplier Mode programming, but can be used to debugging purposes or to reduce calibration time.
8-0UNDISCLOSEDR/W8h Program this field to 0x8.

7.5.1.26 R29 Register (Offset = 1Dh) [Reset = 05FFh]

R29 is shown in Table 7-31.

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Table 7-31 R29 Register Field Descriptions
BitFieldTypeResetDescription
15-13UNDISCLOSEDR0h Program this field to 0x0.
12-8UNDISCLOSEDR/W5h Program this field to 0x5.
7-0VCO_CAPCTRLR/WFFh Sets the starting value for the VCO tuning capacitance during multiplier calibration. Not required for Multiplier Mode programming, but can be used to reduce calibration time.

7.5.1.27 R33 Register (Offset = 21h) [Reset = 7777h]

R33 is shown in Table 7-32.

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Table 7-32 R33 Register Field Descriptions
BitFieldTypeResetDescription
15-0UNDISCLOSEDR/W7777h Program this field to 0x6666. Note that this is different than the reset value.

7.5.1.28 R34 Register (Offset = 22h) [Reset = 0007h]

R34 is shown in Table 7-33.

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Table 7-33 R34 Register Field Descriptions
BitFieldTypeResetDescription
15-14UNDISCLOSEDR0h Program this field to 0x0.
13-0UNDISCLOSEDR/W7h Program this field to 0x5. Note that this is different than the reset value.

7.5.1.29 R65 Register (Offset = 41h) [Reset = 65F0h]

R65 is shown in Table 7-34.

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Table 7-34 R65 Register Field Descriptions
BitFieldTypeResetDescription
15-9UNDISCLOSEDR/W32h Program this field to 0x32.
8-4rb_VCO_CORER1Fh Readback for the multiplier VCO Core. There are only valid values and the VCO is determined by the bit that is low.
Fh = VCO1
17h = VCO2
1Bh = VCO3
1Dh = VCO4
1Eh = VCO5
3-0UNDISCLOSEDR/W0h Program this field to 0x0.

7.5.1.30 R67 Register (Offset = 43h) [Reset = 50C8h]

R67 is shown in Table 7-35.

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Table 7-35 R67 Register Field Descriptions
BitFieldTypeResetDescription
15-0UNDISCLOSEDR/W50C8h Program this field to 0x51CB. Note that this is different than the reset value.

7.5.1.31 R72 Register (Offset = 48h) [Reset = 0000h]

R72 is shown in Table 7-36.

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Table 7-36 R72 Register Field Descriptions
BitFieldTypeResetDescription
15UNDISCLOSEDR0h Program this field to 0x0.
14-3UNDISCLOSEDR/W0h Program this field to 0x0.
2SYSREFREQ_FORCER/W0h Setting this bit emulates the behavior of a logic HIGH at SYSREFREQ pins and causes external signals on SYSREFREQ pins to be ignored.
1-0SYSREF_DLY_BYPR/W0h Option to bypass delay generator retiming. Under normal circumstances (SYSREF_DLY_BYP = 0) the delay generator is engaged for continuous or pulser modes (Generator Modes), and bypassed in Repeater Mode. Generally this typically utilize a different delay mechanism. In certain cases, bypassing the delay generator retiming in Generator Mode by setting SYSREF_DLY_BYP = 1 can substantially reduce the device current consumption if the SYSREF delay can be compensated at the JESD receiver. In other cases, retiming the SYSREFREQ signal to the delay generators by setting SYSREF_DLY_BYP = 2 can improve the accuracy of the SYSREF output phase with respect to the CLKIN phase, or can vary
the delay of individual outputs independently, as long as coherent phase relationship exists between the interpolator divider phase and the SYSREFREQ phase.
0h = Engage in Generator Mode, Bypass in Repeater Mode
1h = Bypass in All Modes
2h = Engage in All Modes
3h = Reserved

7.5.1.32 R73 Register (Offset = 49h) [Reset = 0000h]

R73 is shown in Table 7-37.

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Table 7-37 R73 Register Field Descriptions
BitFieldTypeResetDescription
15-13UNDISCLOSEDR0h Program this field to 0x0.
12-0UNDISCLOSEDR/W0h Program this field to 0x1000. Note that this is different than the reset value.

7.5.1.33 R75 Register (Offset = 4Bh) [Reset = 0006h]

R75 is shown in Table 7-38.

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Table 7-38 R75 Register Field Descriptions
BitFieldTypeResetDescription
15rb_CLK2_ENR0h Readback Pin Status
14rb_CLK1_ENR0h Readback Pin Status
13rb_CLK0_ENR0h Readback Pin Status
12rb_MUXSEL1R0h Readback Pin Status
11rb_MUXSEL0R0h Readback Pin Status
10rb_LOGIC_ENR0h Readback Pin Status
9-8rb_LDR0h Readback for Multiplier PLL lock detect.
0h = Unlocked (VTUNE low)
1h = Reserved
2h = Locked
3h = Unlocked (VTUNE high)
7rb_DIVSEL2R0h Readback Pin Status
6rb_DIVSEL1R0h Readback Pin Status
5rb_DIVSEL0R0h Readback Pin Status
4rb_CER0h Readback Pin Status
3-0UNDISCLOSEDR/W6h Program this field to 0x3. Note that this is different than the reset value.

7.5.1.34 R76 Register (Offset = 4Ch) [Reset = 0000h]

R76 is shown in Table 7-39.

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Table 7-39 R76 Register Field Descriptions
BitFieldTypeResetDescription
15-4UNDISCLOSEDR/W0h Program this field to 0x0.
3rb_PWRSEL2R0h Readback Pin Status
2rb_PWRSEL1R0h Readback Pin Status
1rb_PWRSEL0R0h Readback Pin Status
0rb_CLK3_ENR0h Readback Pin Status

7.5.1.35 R86 Register (Offset = 56h) [Reset = 0000h]

R86 is shown in Table 7-40.

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Table 7-40 R86 Register Field Descriptions
BitFieldTypeResetDescription
15-3UNDISCLOSEDR/W0h Program this field to 0x0.
2MUXOUT_EN_OVRDR/W0h No description
1-0UNDISCLOSEDR/W0h Program this field to 0x0.

7.5.1.36 R90 Register (Offset = 5Ah) [Reset = 0000h]

R90 is shown in Table 7-41.

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Table 7-41 R90 Register Field Descriptions
BitFieldTypeResetDescription
15-8UNDISCLOSEDR0h Program this field to 0x0.
7UNDISCLOSEDR/W0h Program this field to 0x0.
6LOGICLK_DIV_BYP3R/W0h This bit should be set to 1 if LOGICLK_DIV_BYP=1, 0 otherwise.
5LOGICLK_DIV_BYP2R/W0h This bit should be set to 1 if LOGICLK_DIV_BYP=1, 0 otherwise.
4-0UNDISCLOSEDR/W0h Program this field to 0x0.