SNAS851 December   2023 LMX1906-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier
          1. 6.3.3.4.1 General Information about the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Lock Detect for the Clock Multiplier
          5. 6.3.3.4.5 Watchdog Timer
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_FORCE Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
            3. 6.3.6.3.2.3 Other Pointers With SYSREF Windowing
            4. 6.3.6.3.2.4 For Glitch-Free Output
            5. 6.3.6.3.2.5 If Using SYNC Feature
          3. 6.3.6.3.3 SYNC Feature
      7. 6.3.7 Pin Mode Control
        1. 6.3.7.1 Chip Enable (CE)
        2. 6.3.7.2 Output Channel Control
        3. 6.3.7.3 Logic Output Control
        4. 6.3.7.4 SYSREF Output Control
        5. 6.3.7.5 Device Mode Selection
        6. 6.3.7.6 Divider or Multiplier Value Selection
        7. 6.3.7.7 Calibration Control Pin
        8. 6.3.7.8 Output Power Control
  8. 7 Application and Implementation
    1. 7.1 Applications Information
      1. 7.1.1 SYSREFREQ Input Configuration
      2. 7.1.2 Treatment of Unused Pins
      3. 7.1.3 Current Consumption
    2. 7.2 Typical Applications
      1. 7.2.1 Local Oscillator Distribution Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Plots
      2. 7.2.2 JESD204B/C Clock Distribution Application
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Timing
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
    5. 7.5 Register Map
      1. 7.5.1 Device Registers
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Register Map

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWERDOWN 0 RESET
R2 0 0 0 0 0 0 SMCLK_DIV_PRE SMCLK_EN 0 0 0 1 1
R3 CH3_EN CH2_EN CH1_EN CH0_EN LOGICLK_MUTE_CAL CH3_MUTE_CAL CH2_MUTE_CAL CH1_MUTE_CAL CH0_MUTE_CAL 0 0 0 0 SMCLK_DIV
R4 0 0 CLKOUT1_PWR CLKOUT0_PWR SYSREFOUT3_EN SYSREFOUT2_EN SYSREFOUT1_EN SYSREFOUT0_EN CLKOUT3_EN CLKOUT2_EN CLKOUT1_EN CLKOUT0_EN
R5 0 SYSREFOUT2_PWR SYSREFOUT1_PWR SYSREFOUT0_PWR CLKOUT3_PWR CLKOUT2_PWR
R6 LOGICLKOUT_EN SYSREFOUT3_VCM SYSREFOUT2_VCM SYSREFOUT1_VCM SYSREFOUT0_VCM SYSREFOUT3_PWR
R7 0 LOGISYSREFOUT_VCM LOGICLKOUT_VCM LOGISYSREF_DIV_PWR_PRE LOGICLK_DIV_PWR_PRE LOGISYSREFOUT_PWR LOGICLKOUT_PWR LOGISYSREFOUT_EN
R8 0 0 0 0 0 0 0 LOGICLK_DIV_PRE LOGIC_EN 0 LOGISYSREFOUT_FMT LOGICLKOUT_FMT
R9 SYSREFREQ_VCM SYNC_EN LOGICLK_DIV_PD LOGICLK_DIV_BYP 0 LOGICLK_DIV
R11 rb_CLKPOS
R12 rb_CLKPOS[31:16]
R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSREFREQ_DLY_STEP
R14 0 0 0 0 0 0 0 SYNC_MUTE_PD 0 0 0 0 0 CLKPOS_CAPTURE_EN SYSREFREQ_MODE SYSREFREQ_LATCH
R15 0 0 0 0 SYSREF_DIV_PRE 1 SYSREF_EN 0 SYSREFREQ_DLY SYSREFREQ_CLR
R16 SYSREF_PULSE_CNT SYSREF_DIV
R17 0 0 0 0 0 SYSREF0_DLY_I SYSREF0_DLY_PHASE SYSREF_MODE
R18 SYSREF1_DLY_I SYSREF1_DLY_PHASE SYSREF0_DLY_Q
R19 SYSREF2_DLY_I SYSREF2_DLY_PHASE SYSREF1_DLY_Q
R20 SYSREF3_DLY_I SYSREF3_DLY_PHASE SYSREF2_DLY_Q
R21 LOGISYSREF_DLY_I LOGISYSREF_DLY_PHASE SYSREF3_DLY_Q
R22 SYSREF1_DLY_SCALE SYSREF0_DLY_SCALE SYSREF_DLY_DIV 0 0 LOGISYSREF_DLY_Q
R23 TS_EN 1 MUXOUT_EN 0 0 0 0 0 0 MUXOUT_SEL LOGISYSREF_DLY_SCALE SYSREF3_DLY_SCALE SYSREF2_DLY_SCALE
R24 0 0 0 0 rb_TS TS_CNT_EN
R25 0 0 0 0 0 0 1 0 0 CLK_DIV_RST CLK_DIV CLK_MUX
R28 0 0 0 VCO_CORE_FORCE VCO_CORE 0 0 0 0 0 1 0 0 0
R29 0 0 0 0 0 1 0 1 VCO_CAPCTRL
R33 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0
R34 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
R65 0 1 1 0 0 1 0 rb_VCO_CORE 0 0 0 0
R67 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 1
R72 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSREFREQ_FORCE SYSREF_DLY_BYP
R73 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
R75 rb_CLK2_EN rb_CLK1_EN rb_CLK0_EN rb_MUXSEL1 rb_MUXSEL0 rb_LOGIC_EN rb_LD rb_DIVSEL2 rb_DIVSEL1 rb_DIVSEL0 rb_CE 0 0 1 1
R76 0 0 0 0 0 0 0 0 0 0 0 0 rb_PWRSEL2 rb_PWRSEL1 rb_PWRSEL0 rb_CLK3_EN
R79 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
R86 0 0 0 0 0 0 0 0 0 0 0 0 0 MUXOUT_EN_OVRD 0 0
R90 0 0 0 0 0 0 0 0 0 LOGICLK_DIV_BYP3 LOGICLK_DIV_BYP2 0 0 0 0 0
Registers not listed in this table must NOT be programmed as doing so may adversely impact performance or functionality of the device.
The following registers must NOT be programmed as doing show could adversely impact performance of the device: R1, R10, R26, R27, R30-R32,
The following registers do NOT require programming if clock output multiplier is NOT used: R29, R33, R34, R65, R67, R73
The following registers do NOT require programming if LOGICLK is NOT used: R79, R90