LMX243x PLLatinum Dual High-Frequency Synthesizer for RF Personal Communications

1 Features

Low Current Consumption
- LMX2430 (RF/IF): 2.8 mA/ 1.4 mA
- LMX2433 (RF/IF): 3.2 mA/ 2 mA
- LMX2434 (RF/IF): 4.6 mA/ 2.4 mA
2.25-V to 2.75-V Operation
Synchronous/Asynchronous Power Down
Multiple PLL Options:
- LMX2430 (RF/IF): 3 GHz /0.8 GHz
- LMX2433 (RF/IF): 3.6 GHz /1.7 GHz
- LMX2434 (RF/IF): 5 GHz /2.5 GHz
Programmable Charge-Pump Current Levels
- RF and IF: 1 or 4 mA
Fastlock With Integrated Time-Out Counters
Digital Filtered Lock-Detect Output
Analog Lock Detect (Push-Pull / Open-Drain)
1.8-V MICROWIRE Logic Interface

2 Applications

Mobile Handsets
Cordless Handsets
Wireless Data
Cable TV Tuners

3 Description

Using a proprietary digital-phase, locked-loop technique, the LMX243x devices generate very stable, low-noise control signals for RF and IF voltage controlled oscillators. Both the RF and IF synthesizers include a two-level programmable charge pump. Both the RF and IF PLLs have dedicated fastlock circuitry with integrated time-out counters which require only a single word write to power up or change frequencies.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LMX243x	ULGA (20)	3.50 mm × 3.50 mm
LMX243x	TSSOP (20)	6.50 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

NOTE:

1 (2) refers to Pin 1 of the 20-Pin ULGA and Pin 2 of the 20-Pin TSSOP

4 Revision History

Changes from C Revision (March 2013) to D Revision

Shortened data sheet title LMX243x PLLatinum™ Dual High-Frequency Synthesizer for RF Personal Communications LMX2430 3 GHz/0.8 GHz, LMX2433 3.6 GHz/1.7 GHz, LMX2434 5 GHz/2.5 GHz to LMX243x PLLatinum™ Dual High-Frequency Synthesizer for RF Personal Communications because the extra information is also listed in FeaturesGo
Added Device Information table, Pin Configuration and Functions section, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from B Revision (March 2013) to C Revision

Changed layout of National Data Sheet to TI formatGo

5 Description continued

The LMX243x devices are high-performance frequency synthesizers with integrated dual-modulus prescalers. A 32/33 or a 16/17 prescale ratio can be selected for the 5-GHz LMX2434 RF synthesizer. An 8/9 or a 16/17 prescale ratio can be selected for both the LMX2430 and LMX2433 RF synthesizers. The IF circuitry contains an 8/9 or a 16/17 prescaler.

Serial data is transferred to the devices through a three-wire interface (DATA, LE, CLK). A low voltage logic interface allows direct connection to 1.8-V devices. Supply voltages from 2.25 V to 2.75 V are supported.

6 Pin Configuration and Functions

NPE Package

20-Pin ULGA Ultra Thin Chip Scale

Top View

PW Package

20-Pin TSSOP Thin Shrink Small Outline

Top View

Pin Functions

PIN			I/O	DESCRIPTION
NAME	ULGA	TSSOP	I/O	DESCRIPTION
CLK	18	19	I	MICROWIRE Clock input. High-impedance CMOS input. DATA is clocked into the 24-bit shift register on the rising edge of CLK.
CPoutIF	4	5	O	IF PLL charge-pump output. The output is connected to the external loop filter, which drives the input of the IF VCO.
CPoutRF	12	13	O	RF PLL charge-pump output. The output is connected to the external loop filter, which drives the input of the RF VCO.
DATA	19	20	I	MICROWIRE Data input. High-impedance CMOS input. Binary serial data. The MSB of DATA is shifted in first. The two last bits are the control bits.
EN	3	4	I	Chip Enable input. High-Impedance CMOS input. When this pin is set HIGH, the RF and IF PLLs are powered up. Power down is then controlled through the MICROWIRE. When this pin is set LOW, the device is asynchronously powered down, and the charge-pump output is forced to a high-impedance state (tri-state).
ENosc	5	6	I	Oscillator Enable input. High-impedance CMOS input. When this pin is set HIGH, the oscillator buffer is always powered up, independent of the state of the EN pin. When this pin is set LOW, the OSCout/ FLoutIF pin functions as an IF fastlock output, which connects a resistor in parallel to R2 of the external loop filter.
FinIF	2	3	I	IF PLL prescaler input. Small signal input from the VCO.
FLoutRF	10	11	O	RF PLL fastlock output. This pin connects a resistor in parallel to R2 of the external loop filter. This pin can also function as a general-purpose CMOS tri-state output.
FinRF	14	15	I	RF PLL prescaler input. Small-signal input from the VCO.
FinRF*	15	16	I	RF PLL prescaler complementary input. For single-ended operation, this pin must be AC grounded through a 100-pF capacitor. The LMX243x can be driven differentially when the AC-coupled capacitor is omitted.
Ftest/LD	9	10	O	Programmable multiplexed output. Functions as a general-purpose CMOS tri-state output, N and R divider output, RF/ IF PLL push-pull analog lock-detect output, RF/ IF PLL open-drain analog lock-detect output, or RF/ IF PLL digital filtered lock-detect output.
GND	1	2	—	Ground for the IF PLL analog and digital circuits, MICROWIRE, Ftest/LD and oscillator circuits.
	11	12
	13	14
LE	17	18	I	MICROWIRE Latch Enable input. High-impedance CMOS input. When LE transitions HIGH, DATA stored in the shift register is loaded into one of 6 internal control registers.
OSCout/ FLoutIF	6	7	O	Oscillator output/ IF PLL fastlock output. The output configuration is dependent on the state of the ENosc pin. When ENosc is set LOW, the pin functions as an IF fastlock output, which connects a resistor in parallel to R2 of the external loop filter. This configuration also functions as a general-purpose CMOS tri-state output. When ENosc is set HIGH, the pin functions as an oscillator output so that an external crystal can be used.
OSCin	7	8	I	Reference oscillator input. The input has an approximate Vcc/2 threshold and is driven by an external AC-coupled source.
Vcc	16	17	—	Power supply bias for the RF PLL analog circuits. Vcc may range from 2.25 V to 2.75 V. Bypass capacitors must be placed as close as possible to this pin and be connected directly to the ground plane.
	8	9
	20	1