SNAS236 Data sheet

SNAS236G October 2005 – January 2016 LMX2485 , LMX2485E

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTW|24
- MPQF167C

サーマルパッド・メカニカル・データ

RTW|24
- QFND450A

8 Detailed Description

8.1 Overview

The LMX2485 consists of integrated N counters, R counters, and charge pumps. The TCXO, VCO and loop filter are supplied external to the chip.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 TCXO, Oscillator Buffer, and R Counter

The oscillator buffer must be driven single-ended by a signal source, such as a TCXO. The OSCout pin is included to provide a buffered output of this input signal and is active when the OSC_OUT bit is set to one. The ENOSC pin can be also pulled high to ensure that the OSCout pin is active, regardless of the status of the registers in the LMX2485.

The R counter divides this TXCO frequency down to the comparison frequency.

8.3.2 Phase Detector

The maximum phase detector operating frequency for the IF PLL is straightforward, but it is a little more involved for the RF PLL because it is fractional. The maximum phase detector frequency for the LMX2485 RF PLL is 50 MHz. However, this is not possible in all circumstances due to illegal divide ratios of the N counter. The crystal reference frequency also limits the phase detector frequency, although the doubler helps with this limitation. There are trade-offs in choosing the phase detector frequency. If this frequency is run higher, then phase noise will be lower, but lock time may be increased due to cycle slipping and the capacitors in the loop filter may become rather large.

8.3.3 Charge Pump

For the majority of the time, the charge pump output is high impedance, and the only current through this pin is the Tri-State leakage. However, it does put out fast correction pulses that have a width that is proportional to the phase error presented at the phase detector.

The charge pump converts the phase error presented at the phase detector into a correction current. The magnitude of this current is theoretically constant, but the duty cycle is proportional to the phase error. For the IF PLL, this current is not programmable, but for the RF PLL it is programmable in 16 steps. Also, the RF PLL allows for a higher charge pump current to be used when the PLL is locking to reduce the lock time.

8.3.4 Loop Filter

The loop filter design can be rather involved. In addition to the regular constraints and design parameters, delta-sigma PLLs have the additional constraint that the order of the loop filter should be one greater than the order of the delta sigma modulator. This rule of thumb comes from the requirement that the loop filter must roll off the delta sigma noise at 20 dB/decade faster than it rises. However, because the noise can not have infinite power, it must eventually roll off. If the loop bandwidth is narrow, this requirement may not be necessary. For the purposes of discussion in this data sheet, the pole of the loop filter at 0 Hz is not counted. So a second order filter has 3 components, a 3rd order loop filter has 5 components, and the 4th order loop filter has 7 components. Although a 5th order loop filter is theoretically necessary for use with a 4th order modulator, typically a 4th order filter is used in this case. The loop filter design, especially for higher orders can be rather involved, but there are many simulation tools and references available, such as the one given at the end of the functional description block.

8.3.5 N Counters and High Frequency Input Pins

The N counter divides the VCO frequency down to the comparison frequency. Because prescalers are used, there are limitations on how small the N value can be. The N counters are discussed in greater depth in the programming section. Because the input pins to these counters (FinRF and FinIF) are high frequency, layout considerations are important.

8.3.5.1 High Frequency Input Pins, FinRF and FinIF

TI recommends that the VCO output go through a resistive pad and then through a DC-blocking capacitor before it gets to these high frequency input pins. If the trace length is sufficiently short (< 1/10th of a wavelength), then the pad may not be necessary, but a series resistor of about 39 Ω is still recommended to isolate the PLL from the VCO. The DC-blocking capacitor should be chosen at least to be 27 pF, depending on frequency. It may turn out that the frequency is above the self-resonant frequency of the capacitor, but because the input impedance of the PLL tends to be capacitive, it actually is a benefit to exceed the tune frequency. The pad and the DC-blocking capacitor should be placed as close to the PLL as possible

8.3.5.2 Complementary High Frequency Pin, FinRF*

These inputs may be used to drive the PLL differentially, but it is very common to drive the PLL in a single ended fashion. A shunt capacitor should be placed at the FinRF* pin. The value of this capacitor should be chosen such that the impedance, including the ESR of the capacitor, is as close to an AC short as possible at the operating frequency of the PLL. 100 pF is a typical value, depending on frequency.

8.3.6 Digital Lock Detect Operation

The RF PLL digital lock detect circuitry compares the difference between the phase of the inputs of the phase detector to a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less than the ε RC delay for 5 consecutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater δ. The values of ε and δ are dependent on which PLL is used and are shown in Table 6:

Table 6. Digital Lock Detection Tolerances

PLL	ε	δ
RF	10 ns	20 ns
IF	15 ns	30 ns

When the PLL is in the power-down mode and the Ftest/LD pin is programmed for the lock detect function, it is forced LOW. The accuracy of this circuit degrades at higher comparison frequencies. To compensate for this, the DIV4 word should be set to one if the comparison frequency exceeds 20 MHz. The function of this word is to divide the comparison frequency presented to the lock detect circuit by 4. If the MUX[3:0] word is set such as to view lock detect for both PLLs, an unlocked (LOW) condition is shown whenever either one of the PLLs is determined to be out of lock.

8.3.7 Cycle Slip Reduction and Fastlock

The LMX2485 offers both cycle slip reduction (CSR) and Fastlock with time-out counter support. This means that it requires no additional programming overhead to use them. TI recommends that the charge pump current in the steady-state be 8X or less to use cycle slip reduction, and 4X or less in steady-state to use Fastlock. The next step is to decide between using Fastlock or CSR. This determination can be made based on the ratio of the comparison frequency (f_COMP) to loop bandwidth (BW).

Table 7. Using Cycle Slip Reduction and Fastlock

COMPARISON FREQUENCY (f_COMP)	FASTLOCK	CYCLE SLIP REDUCTION (CSR)
f_COMP ≤ 1.25 MHz	Noticeable better than CSR	Likely to provide a benefit, provided that f_COMP > 100 X BW
1.25 MHz < f_COMP ≤ 2 MHz	Marginally better than CSR
f_COMP > 2 MHz	Same or worse than CSR

8.3.7.1 Cycle Slip Reduction (CSR)

Cycle slip reduction works by reducing the comparison frequency during frequency acquisition while keeping the same loop bandwidth, thereby reducing the ratio of the comparison frequency to the loop bandwidth. In cases where the ratio of the comparison frequency exceeds about 100 times the loop bandwidth, cycle slipping can occur and significantly degrade lock times. The greater this ratio, the greater the benefit of CSR. This is typically the case of high comparison frequencies. In circumstances where there is not a problem with cycle slipping, CSR provides no benefit. There is a glitch when CSR is disengaged, but because CSR should be disengaged long before the PLL is actually in lock, this glitch is not an issue. A good rule of thumb for CSR disengagement is to do this at the peak time of the transient response. Because this time is typically much sooner than Fastlock should be disengaged, it does not make sense to use CSR and Fastlock in combination.

8.3.7.2 Fastlock

Fastlock works by increasing the loop bandwidth only during frequency acquisition. In circumstances where the comparison frequency is less than or equal to 2 MHz, Fastlock may provide a benefit beyond what CSR can offer. Because Fastlock also reduces the ratio of the comparison frequency to the loop bandwidth, it may provide a significant benefit in cases where the comparison frequency is greater than 2 MHz. However, CSR can usually provide an equal or larger benefit in these cases, and can be implemented without using an additional resistor. The reason for this restriction on frequency is that Fastlock has a glitch when it is disengaged. As the time of engagement for Fastlock decreases and becomes on the order of the fast lock time, this glitch grows and limits the benefits of Fastlock. This effect becomes worse at higher comparison frequencies. There is always the option of reducing the comparison frequency at the expense of phase noise to satisfy this constraint on comparison frequency. Despite this glitch, there is still a net improvement in lock time using Fastlock in these circumstances. When using Fastlock, TI also recommends that the steady-state charge pump state be 4X or less. Also, Fastlock was originally intended only for second order filters, so when implementing it with higher order filters, the third and fourth poles can not be too close in, or it will not be possible to keep the loop filter well optimized when the higher charge pump current and Fastlock resistor are engaged.

8.3.7.3 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping

Once it is decided that CSR is to be used, the cycle slip reduction factor needs to be chosen. The available factors are 1/2, 1/4, and 1/16. To preserve the same loop characteristics, TI recommends that the following constraint be satisfied:

8.3.7.3.1 (Fastlock Charge Pump Current) / (Steady-State Charge Pump Current) = CSR

To satisfy this constraint, the maximum charge pump current in steady-state is 8X for a CSR of 1/2, 4X for a CSR of 1/4, and 1X for a CSR of 1/16. Because the PLL phase noise is better for higher charge pump currents, it makes sense to choose CSR only as large as necessary to prevent cycle slipping. Choosing it larger than this will not improve lock time, and will result in worse phase noise.

Consider an example where the desired loop bandwidth in steady-state is 100 kHz and the comparison frequency is 20 MHz. This yields a ratio of 200. Cycle slipping may be present, but would not be too severe if it was there. If a CSR factor of 1/2 is used, this would reduce the ratio to 100 during frequency acquisition, which is probably sufficient. A charge pump current of 8X could be used in steady-state, and a factor of 16X could be used during frequency acquisition. This yields a ratio of 1/2, which is equal to the CSR factor and this satisfies the above constraint. In this circumstance, it could also be decided to just use 16X charge pump current all the time, because it would probably have better phase noise, and the degradation in lock time would not be too severe.

8.3.7.4 Using Fastlock to Improve Lock Times

Figure 23. Loop Filter with Fastlock Resistor

Once it is decided that Fastlock is to be used, the loop bandwidth multiplier, K, is needed to determine the theoretical impact of Fastlock on the loop bandwidth and the resistor value, R2p, that is switched in parallel during Fastlock. This ratio is calculated as follows:

Table 8. K = (Fastlock Charge Pump Current) / (Steady-State Charge Pump Current)

K	LOOP BANDWIDTH	R2p VALUE	LOCK TIME
1	1.00 X	Open	100%
2	1.41 X	R2/0.41	71%
3	1.73 X	R2/0.73	58%
4	2.00 X	R2	50%
8	2.83 X	R2/1.83	35%
9	3.00 X	R2/2	33%
16	4.00 X	R2/3	25%

Table 8 shows how to calculate the Fastlock resistor and theoretical lock time improvement, once the ratio , K, is known. This all assumes a second order filter (not counting the pole at 0 Hz). However, TI generally recommends that the loop filter order be one greater than the order of the delta sigma modulator, which means that a second order filter is never recommended. In this case, the value for R2p is typically about 80% of what it would be for a second order filter. Because the Fastlock disengagement glitch gets larger and it is harder to keep the loop filter optimized as the K value becomes larger, designing for the largest possible value for K usually, but not always yields the best improvement in lock time. To get a more accurate estimate requires more simulation tools, or trial and error.

8.3.7.5 Capacitor Dielectric Considerations for Lock Time

The LMX2485 has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value. For larger capacitor values, it is common to have a trade-off between capacitor dielectric quality and physical size. Using film capacitors or NPO/COG capacitors yields the best possible lock times, where as using X7R or Z5R capacitors can increase lock time by 0 – 500%. However, it is a general tendency that designs that use a higher compare frequency tend to be less sensitive to the effects of capacitor dielectrics. Although the use of lesser quality dielectric capacitors may be unavoidable in many circumstances, allowing a larger footprint for the loop filter capacitors, using a lower charge pump current, and reducing the fractional modulus are all ways to reduce capacitor values. Capacitor dielectrics have very little impact on phase noise and spurs.

8.3.8 Fractional Spur and Phase Noise Controls

Control of the fractional spurs is more of an art than an exact science. The first differentiation that needs to be made is between primary fractional and sub-fractional spurs. The primary fractional spurs are those that occur at increments of the channel spacing only. The sub-fractional spurs are those that occur at a smaller resolution than the channel spacing, usually one-half or one-fourth. There are trade-offs between fractional spurs, sub-fractional spurs, and phase noise. The rules of thumb presented in this section are just that. There will be exceptions. The bits that impact the fractional spurs are FM and DITH, and these bits should be set in this order.

The first step to do is choose FM, for the delta sigma modulator order. TI recommends to start with FM = 3 for a third order modulator and use strong dithering. In general, there is a trade-off between primary and sub-fractional spurs. Choosing the highest order modulator (FM = 0 for 4th order) typically provides the best primary fractional spurs, but the worst sub-fractional spurs. Choosing the lowest modulator order (FM = 2 for 2nd order), typically gives the worst primary fractional spurs, but the best sub-fractional spurs. Choosing FM = 3, for a 3rd order modulator is a compromise.

The second step is to choose DITH, for dithering. Dithering has a very small impact on primary fractional spurs, but a much larger impact on sub-fractional spurs. The only problem is that it can add a few dB of phase noise, or even more if the loop bandwidth is very wide. Disabling dithering (DITH = 0), provides the best phase noise, but the sub-fractional spurs are worst (except when the fractional numerator is 0, and in this case, they are the best). Choosing strong dithering (DITH = 2) significantly reduces sub-fractional spurs, if not eliminating them completely, but adds the most phase noise. Weak dithering (DITH = 1) is a compromise.

The third step is to tinker with the fractional word. Although 1/10 and 400/4000 are mathematically the same, expressing fractions with much larger fractional numerators often improve the fractional spurs. Increasing the fractional denominator only improves spurs to a point. A good practical limit could be to keep the fractional denominator as large as possible, but not to exceed 4095, so it is not necessary to use the extended fractional numerator or denominator.

This steps can be done in different orders and it might take a few iterations to find the optimum performance. Special considerations should be taken for lower frequencies that are less than 100 MHz. In addition squaring up the wave, it is often helpful to use lowest terms fractions instead of highest terms fractions. Also, dithering may turn out to not be so useful. All the things are to introduce a methodical way of thinking about optimizing spurs, not an exact method. There will be exceptions to all these rules.

NOTE

For more information concerning delta-sigma PLLs, loop filter design, cycle slip reduction, Fastlock, and many other topics, visit www.ti.com. Here there is the EasyPLL simulation tool and an online reference called PLL Performance, Simulation, and Design.

8.4 Device Functional Modes

8.4.1 Power Pins, Power-Down, and Power-Up Modes

TI recommends that all of the power pins be filtered with a series 18-Ω resistor and then placing two capacitors shunt to ground, thus creating a low pass filter. Although it makes sense to use large capacitor values in theory, the ESR (Equivalent Series Resistance) is greater for larger capacitors. For optimal filtering minimize the sum of the ESR and theoretical impedance of the capacitor. Therefore TI recommends to provide two capacitors of very different sizes for the best filtering. 1 µF and 100 pF are typical values. The small capacitor should be placed as close as possible to the pin.

The power down state of the LMX2485 is controlled by many factors. The one factor that overrides all other factors is the CE pin. If this pin is low, the part will be powered down. Asserting a high logic level on this pin is necessary to power up the chip, however, there are other bits in the programming registers that can override this and put the PLL back in a power-down state. Provided that the voltage on the CE pin is high, programming the RF_PD and IF_PD bits to zero ensures that the part will be powered up. Programming either one of these bits to one will power down the appropriate section of the synthesizer, provided that the ATPU bit does not override this.

Table 9. Power-Up and Down States

CE PIN	RF_PD	ATPU Bit Enabled + N Counter Write	PLL STATE
Low	X	X	Powered Down (Asynchronous)
High	X	Yes	Powered Up
High	0	No	Powered Up
High	1	No	Powered Down (Asynchronous)

8.5 Programming

8.5.1 General Programming Information

The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter, the N counter, and the internal mode control latches. The data format of a typical 24-bit data register is shown in Table 10. The control bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift register is loaded into one of the appropriate latches (selected by address bits). Data is shifted in MSB first.

NOTE

It is best to program the N counter last, because doing so initializes the digital lock detector and Fastlock circuitry. Initialize means it resets the counters, but it does NOT program values into these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program the R7 register.

Table 10. Register Structure

MSB		LSB
DATA [21:0]		CTL [3:0]
23	4	3	2	1	0

8.5.1.1 Register Location Truth Table

The control bits CTL [3:0] decode the internal register address. Table 11 shows how the control bits are mapped to the target control register.

Table 11. Programmable Registers

C3	C2	C1	C0	DATA LOCATION
x	x	x	0	R0
0	0	1	1	R1
0	1	0	1	R2
0	1	1	1	R3
1	0	0	1	R4
1	0	1	1	R5
1	1	0	1	R6
1	1	1	1	R7

8.5.1.2 Control Register Content Map

Because the LMX2485 registers are complicated, they are organized into two groups, basic and advanced. The first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that optimize spur, phase noise, and lock time performance. The next page shows these registers.

8.5.1.3 Quick Start Register Map

Although TI highly recommends that the user eventually take advantage of all the modes of the LMX2485, the quick start register map is shown in order for the user to get the part up and running quickly using only those bits critical for basic functionality. The following default conditions for this programming state are a third order delta-sigma modulator in 12-bit mode with no dithering and no Fastlock.

Table 12. Quick Start Register Map

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0] (Except for the RF_N Register, which is [22:0])																				C3	C2	C1	C0
R0	RF_N[10:0]											RF_FN[11:0]												0
R1	RF_PD	RF_P	RF_R[5:0]						RF_FD[11:0]												0	0	1	1
R2	IF_PD	IF_N[18:0]																			0	1	0	1
R3	0001				RF_CPG[3:0]				IF_R[11:0]												0	1	1	1
R4	0	0	1	0	0	0	0	0	1	1	0	0	0	1	1	1	0	0	0	0	1	0	0	1

8.5.1.4 Complete Register Map

The complete register map shows all the functionality of all registers, including the last five.

Table 13. Complete Register Map

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0] (Except for the RF_N Register, which is [22:0])																				C3	C2	C1	C0
R0	RF_N[10:0]											RF_FN[11:0]												0
R1	RF_PD	RF_P	RF_R[5:0]						RF_FD[11:0]												0	0	1	1
R2	IF_PD	IF_N[18:0]																			0	1	0	1
R3	ACCESS[3:0]				RF_CPG[3:0]				IF_R[11:0]												0	1	1	1
R4	ATPU	0	1	0	0	0	DITH [1:0]		FM [1:0]		0	OSC _2X	OSC _OUT	IF_ CPP	RF_ CPP	IF_P	MUX [3:0]				1	0	0	1
R5	RF_FD[21:12]										RF_FN[21:12]										1	0	1	1
R6	CSR[1:0]		RF_CPF[3:0]				RF_TOC[13:0]														1	1	0	1
R7	0	0	0	0	0	0	0	0	0	0	DIV4	0	1	0	0	1	IF_ RST	RF_ RST	IF_ CPT	RF_ CPT	1	1	1	1

8.6 Register Maps

8.6.1 R0 Register

NOTE

This register has only one control bit, so the N counter value to be changed with a single write statement to the PLL.

Table 14. R0 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[22:0]																							C0
R0	RF_N[10:0]											RF_FN[11:0]												0

8.6.1.1 RF_FN[11:0]—Fractional Numerator for RF PLL

Refer to Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] } for a more detailed description of this control word.

8.6.1.2 RF_N[10:0]—RF N Counter Value

The RF N counter contains an 8/9/12/13 and a 16/17/20/21 prescaler. The N counter value can be calculated as follows:

N = RF_P·RF_C + 4·RF_B + RF_A

RF_C ≥Max{RF_A, RF_B} , for N-2^FM-1 ... N+2^FM is a necessary condition. This rule is slightly modified in the case where the RF_B counter has an unused bit, where this extra bit is used by the delta-sigma modulator for the purposes of modulation. Consult the tables below for valid operating ranges for each prescaler.

Table 15. Operation With the 8/9/12/13 Prescaler (RF_P=0)

RF_N	RF_N [10:0]
RF_N	RF_C [6:0]							RF_B [1:0]		RF_A [1:0]
<25	N values less than 25 are prohibited.
25-26	Possible only with a second order delta-sigma engine.
27-30	Possible only with a second or third order delta-sigma engine.
31	0	0	0	0	0	1	1	0	1	1	1
...	.	.	.	.	.	.	.	0	.	.	.
1023	1	1	1	1	1	1	1	0	1	1	1
>1023	N values greater than 1023 are prohibited.

Table 16. Operation With the 16/17/20/21 Prescaler (RF_P=1)

RF_N	RF_N [10:0]
RF_N	RF_C [6:0]							RF_B [1:0]		RF_A [1:0]
<49	N values less than 49 are prohibited.
49-50	Possible only with a second order delta-sigma engine.
51-54	Possible with a second or third order delta-sigma engine.
55	0	0	0	0	0	1	1	0	1	1	1
...	.	.	.	.	.	.	.	.	.	.	.
2039	1	1	1	1	1	1	1	0	1	1	1
2040-2043	Possible with a second or third order delta-sigma engine.
2044-2045	Possible only with a second order delta-sigma engine.
>2045	N values greater than 2045 are prohibited.

8.6.2 R1 Register

Table 17. R1 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0]																				C3	C2	C1	C0
R1	RF_PD	RF_P	RF_R[5:0]						RF_FD[11:0]												0	0	1	1

8.6.2.1 RF_FD[11:0]—RF PLL Fractional Denominator

The function of these bits are described in Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], Access[1]}.

8.6.2.2 RF_R [5:0]—RF R Divider Value

The RF R Counter value is determined by this control word.

NOTE

This counter does allow values down to one.

Table 18. RF_R [5:0]—RF R Divider Value

R VALUE	RF_R[5:0]
1	0	0	0	0	0	1
...	.	.	.	.	.	.
63	1	1	1	1	1	1

8.6.2.3 RF_P—RF Prescaler Bit

The prescaler used is determined by this bit.

Table 19. RF_P—RF Prescaler Bit

RF_P	PRESCALER	MAXIMUM FREQUENCY
0	8/9/12/13	2000 MHz
1	16/17/20/21	3000 MHz

8.6.2.4 RF_PD—RF Power-Down Control Bit

When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and the RF Charge pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions, and will override the RF_PD bit. The order of precedence is as follows. First, if the CE pin is LOW, then the PLL will be powered down. Provided this is not the case, the PLL will be powered up if the ATPU bit says to do so, regardless of the state of the RF_PD bit. After the CE pin and the ATPU bit are considered, then the RF_PD bit then takes control of the power-down function for the RF PLL.

8.6.3 R2 Register

Table 20. R2 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0]																				C3	C2	C1	C0
R2	IF_PD	IF_N[18:0]																			0	1	0	1

8.6.3.1 IF_N[18:0]—IF N Divider Value

Table 21. IF_N Counter Programming With the 8/9 Prescaler (IF_P=0)

N VALUE	IF_N[18:0]
N VALUE	IF_B															IF_A
≤23	N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
24-55	Legal divide ratios in this range are: 24-27, 32-36, 40-45, 48-54
56	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	0	0	0
57	0	0	0	0	0	0	0	0	0	0	0	0	1	1	1	0	0	0	1
...	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.
262143	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	0	1	1	1

Table 22. Operation With the 16/17 Prescaler (IF_P=1)

N VALUE	IF_B															IF_A
≤47	N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
48-239	Legal divide ratios in this range are: 48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
240	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	0	0	0
241	0	0	0	0	0	0	0	0	0	0	0	1	1	1	1	0	0	0	1
...	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.
524287	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

8.6.3.2 IF_PD—IF Power Down Bit

When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written to, the IF_PD will be reset to 0 and the IF PLL will be powered up. If the CE pin is held low, the IF PLL will be powered down, overriding the IF_PD bit.

8.6.4 R3 Register

Table 23. R3 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0]																				C3	C2	C1	C0
R3	ACCESS[3:0]				RF_CPG[3:0]				IF_R[11:0]												0	1	1	1

8.6.4.1 IF_R[11:0]—IF R Divider Value

For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for IF_R is 3.

Table 24. IF_R[11:0]—IF R Divider Value

R VALUE	IF_R[11:0]
3	0	0	0	0	0	0	0	0	0	0	1	1
...	.	.	.	.	.	.	.	.	.	.	.	.
4095	1	1	1	1	1	1	1	1	1	1	1	1

8.6.4.2 RF_CPG—RF PLL Charge Pump Gain

This is used to control the magnitude of the RF PLL charge pump in steady-state operation.

Table 25. RF_CPG—RF PLL Charge Pump Gain

RF_CPG	CHARGE PUMP STATE	TYPICAL RF CHARGE PUMP CURRENT AT 3 V (µA)
0	1X	95
1	2X	190
2	3X	285
3	4X	380
4	5X	475
5	6X	570
6	7X	665
7	8X	760
8	9X	855
9	10X	950
10	11X	1045
11	12X	1140
12	13X	1235
13	14X	1330
14	15X	1425
15	16X	1520

8.6.4.3 ACCESS—Register Access Word

It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional. The ACCESS[3:0] bits determine which additional registers must be programmed. Any one of these registers can be individually programmed. According to Table 26, when the state of a register is in default mode, all the bits in that register are forced to a default state and it is not necessary to program this register. When the register is programmable, it needs to be programmed through the MICROWIRE. Using this register access technique, the programming required is reduced up to 37%.

Table 26. ACCESS—Register Access Word

ACCESS BIT	REGISTER LOCATION	REGISTER CONTROLLED
ACCESS[0]	R3[20]	Must be set to 1
ACCESS[1]	R3[21]	R5
ACCESS[2]	R3[22]	R6
ACCESS[3]	R3[23]	R7

The default conditions the registers is shown in Table 27:

Table 27. R4 – R7 Registers

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	Data[19:0]																				C3	C2	C1	C0
R4	R4 Must be programmed manually.
R5	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	1
R6	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	1
R7	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	1	0	0	0	0	1	1	1	1

This corresponds to the following bit settings.

Table 28. R4 – R7 Register Descriptions

REGISTER	BIT LOCATION	BIT NAME	BIT DESCRIPTION	BIT VALUE	BIT STATE
R4	R4[23]	ATPU	Autopowerup	0	Disabled
	R4[17:16]	DITH	Dithering	2	Strong
	R4[15:14]	FM	Modulation Order	3	3rd Order
	R4[12]	OSC_2X	Oscillator Doubler	0	Disabled
	R4[11]	OSC_OUT	OSCout Pin Enable	0	Disabled
	R4[10]	IF_CPP	IF Charge Pump Polarity	1	Positive
	R4[9]	RF_CPP	RF Charge Pump Polarity	1	Positive
	R4[8]	IF_P	IF PLL Prescaler	1	16/17
	R4[7:4]	MUX	Ftest/LD Output	0	Disabled
R5	R5[23:14]	RF_FD[21:12]	Extended Fractional Denominator	0	Disabled
R5	R5[13:4]	RF_FN[21:12]	Extended Fractional Numerator	0	Disabled
R6	R6[23:22]	CSR	Cycle Slip Reduction	0	Disabled
	R6[21:18]	RF_CPF	Fastlock Charge Pump Current	0	Disabled
	R6[17:4]	RF_TOC	RF Time-out Counter	0	Disabled
R7	R7[13]	DIV4	Lock Detect Adjustment	0	Disabled (Fcomp ≤ 20 MHz)
	R7[7]	IF_RST	IF PLL Counter Reset	0	Disabled
	R7[6]	RF_RST	RF PLL Counter Reset	0	Disabled
	R7[5]	IF_CPT	IF PLL Tri-State	0	Disabled
	R7[4]	RF_CPT	RF PLL Tri-State	0	Disabled

8.6.5 R4 Register

This register controls the conditions for the RF PLL in Fastlock.

Table 29. R4 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0]																				C3	C2	C1	C0
R4	ATPU	0	1	0	0	0	DITH [1:0]		FM [1:0]		0	OSC_ 2X	OSC_ OUT	IF_ CPP	RF_ CPP	IF_P	MUX [3:0]				1	0	0	1

8.6.5.1 MUX[3:0] Frequency Out and Lock Detect MUX

These bits determine the output state of the Ftest/LD pin.

Table 30. MUX[3:0] Frequency Out and Lock Detect MUX

MUX[3:0]				OUTPUT TYPE	OUTPUT DESCRIPTION
0	0	0	0	High Impedance	Disabled
0	0	0	1	Push-Pull	General-purpose output, Logical “High” State
0	0	1	0	Push-Pull	General-purpose output, Logical “Low” State
0	0	1	1	Push-Pull	RF and IF Digital Lock Detect
0	1	0	0	Push-Pull	RF Digital Lock Detect
0	1	0	1	Push-Pull	IF Digital Lock Detect
0	1	1	0	Open-Drain	RF and IF Analog Lock Detect
0	1	1	1	Open-Drain	RF Analog Lock Detect
1	0	0	0	Open-Drain	IF Analog Lock Detect
1	0	0	1	Push-Pull	RF and IF Analog Lock Detect
1	0	1	0	Push-Pull	RF Analog Lock Detect
1	0	1	1	Push-Pull	IF Analog Lock Detect
1	1	0	0	Push-Pull	IF R Divider divided by 2
1	1	0	1	Push-Pull	IF N Divider divided by 2
1	1	1	0	Push-Pull	RF R Divider divided by 2
1	1	1	1	Push-Pull	RF N Divider divided by 2

8.6.5.2 IF_P—IF Prescaler

When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.

Table 31. IF_P—IF Prescaler

IF_P	IF Prescaler	MAXIMUM FREQUENCY
0	8/9	800 MHz
1	16/17	800 MHz

8.6.5.3 RF_CPP—RF PLL Charge Pump Polarity

Table 32. RF_CPP—RF PLL Charge Pump Polarity

RF_CPP	RF CHARGE PUMP POLARITY
0	Negative
1	Positive (Default)

8.6.5.4 IF_CPP—IF PLL Charge Pump Polarity

For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase detector polarity.

Table 33. IF_CPP—IF PLL Charge Pump Polarity

IF_CPP	IF CHARGE PUMP POLARITY
0	Negative
1	Positive

8.6.5.5 OSC_OUT Oscillator Output Buffer Enable

Table 34. OSC_OUT Oscillator Output Buffer Enable

OSC_OUT	OSCout PIN
0	Disabled (High Impedance)
1	Buffered output of OSCin pin

8.6.5.6 OSC2X—Oscillator Doubler Enable

When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency presented to the RF R counter is doubled. Phase noise added by the doubler is negligible.

Table 35. OSC2X—Oscillator Doubler Enable

OSC2X	FREQUENCY PRESENTED TO RF R COUNTER	FREQUENCY PRESENTED TO IF R COUNTER
0	f_OSCin	f_OSCin
1	2 x f_OSCin	f_OSCin

8.6.5.7 FM[1:0]—Fractional Mode

Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least one greater than the order of the delta-sigma modulator to allow for sufficient roll-off.

Table 36. FM[1:0]—Fractional Mode

FM	FUNCTION
0	Fractional PLL mode with a 4th order delta-sigma modulator
1	Disable the delta-sigma modulator. Recommended for test use only.
2	Fractional PLL mode with a 2nd order delta-sigma modulator
3	Fractional PLL mode with a 3rd order delta-sigma modulator

8.6.5.8 DITH[1:0]—Dithering Control

Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance.

Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional spurs much, but has a much larger impact on the sub-fractional spurs. If it is decided that dithering will be used, best results will be obtained when the fractional denominator is at least 1000.

Table 37. DITH[1:0]—Dithering Control

DITH	DITHERING MODE USED
0	Disabled
1	Weak Dithering
2	Strong Dithering
3	Reserved

8.6.5.9 ATPU—PLL Automatic Power Up

When this bit is set to 1, both the RF and IF PLL when the R0 register is written to. When the R0 register is written to, the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when the CE pin is low. In this case, the ATPU function is disabled.

8.6.6 R5 Register

Table 38. R5 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0]																				C3	C2	C1	C0
R5	RF_FD[21:12]										RF_FN[21:12]										1	0	1	1

8.6.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] }

In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] bits become do not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from 12 to 22-bits.

Table 39. Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], Access[1] }

FRACTIONAL	RF_FN[21:12]										RF_FN[11:0]
NUMERATOR	(THESE BITS ONLY APPLY IN 22-BIT MODE)										RF_FN[11:0]
0	In 12-bit mode, these are do not care. In 22-bit mode, for N <4096, these bits should be all set to 0.										0	0	0	0	0	0	0	0	0	0	0	0
1											0	0	0	0	0	0	0	0	0	0	0	1
...											.	.	.	.	.	.	.	.	.	.	.	.
4095											1	1	1	1	1	1	1	1	1	1	1	1
4096	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
...	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.
4194303	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

8.6.6.2 Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], Access[1]}

In the case that the ACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the RF_FD[21:12] bits become do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode and the fractional denominator is expanded from 12 to 22-bits.

Table 40. Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], Access[1]}

FRACTIONAL	RF_FD[21:12]										RF_FD[11:0]
DENOMINATOR	(These bits only apply in 22-bit mode)										RF_FD[11:0]
0	In 12-bit mode, these are do not care. In 22-bit mode, for N <4096, these bits should be all set to 0.										0	0	0	0	0	0	0	0	0	0	0	0
1											0	0	0	0	0	0	0	0	0	0	0	1
...											.	.	.	.	.	.	.	.	.	.	.	.
4095											1	1	1	1	1	1	1	1	1	1	1	1
4096	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
...	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.	.
4194303	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

8.6.7 R6 Register

Table 41. R6 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DATA[19:0]																				C3	C2	C1	C0
R6	CSR[1:0]		RF_CPF[3:0]				RF_TOC[13:0]														1	1	0	1

8.6.7.1 RF_TOC—RF Time Out Counter and Control for FLoutRF Pin

The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of the FLoutRF output pin. When this word is set to a value between 0 and 3, the RF Fastlock circuitry is disabled and the FLoutRF pin operates as a general-purpose CMOS TRI-STATE I/O. When RF_TOC is set to a value between 4 and 16383, the RF Fastlock mode is enabled and the FLoutRF pin is used as the RF Fastlock output pin. The value programmed into the RF_TOC[13:0] word represents two times the number of phase detector comparison cycles the RF synthesizer will spend in the Fastlock state.

Table 42. RF_TOC—RF Time Out Counter and Control for FLoutRF Pin

RF_TOC	FASTLOCK MODE	FASTLOCK PERIOD [CP EVENTS]	FLoutRF PIN FUNCTIONALITY
0	Disabled	N/A	High Impedance
1	Manual	N/A	Logic “0” State. Forces all Fastlock conditions
2	Disabled	N/A	Logic “0” State
3	Disabled	N/A	Logic “1” State
4	Enabled	4X2 = 8	Fastlock
5	Enabled	5X2 = 10	Fastlock
…	Enabled	…	Fastlock
16383	Enabled	16383X2 = 32766	Fastlock

8.6.7.2 RF_CPF—RF PLL Fastlock Charge Pump Current

Specify the charge pump current for the Fastlock operation mode for the RF PLL.

NOTE

The Fastlock charge pump current, steady-state current, and CSR control are all interrelated.

Table 43. RF_CPF—RF PLL Fastlock Charge Pump Current

RF_CPF	RF CHARGE PUMP STATE	TYPICAL RF CHARGE PUMP CURRENT AT 3 V (µA)
0	1X	95
1	2X	190
2	3X	285
3	4X	380
4	5X	475
5	6X	570
6	7X	665
7	8X	760
8	9X	855
9	10X	950
10	11X	1045
11	12X	1140
12	13X	1235
13	14X	1330
14	15X	1425
15	16X	1520

8.6.7.3 CSR[1:0]—RF Cycle Slip Reduction

CSR controls the operation of the Cycle Slip Reduction Circuit. This circuit can be used to reduce the occurrence of phase detector cycle slips.

NOTE

The Fastlock charge pump current, steady-state current, and CSR control are all interrelated. Refer to Cycle Slip Reduction and Fastlock for information on how to use this.

Table 44. CSR[1:0]—RF Cycle Slip Reduction

CSR	CSR STATE	SAMPLE RATE REDUCTION FACTOR
0	Disabled	1
1	Enabled	1/2
2	Enabled	1/4
3	Enabled	1/16

8.6.8 R7 Register

Table 45. R7 Register

REGISTER	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	Data[19:0]																				C3	C2	C1	C0
R7	0	0	0	0	0	0	0	0	0	0	DIV4	0	1	0	0	1	IF_RST	RF_RST	IF_CPT	RF_CPT	1	1	1	1

8.6.8.1 DIV4—RF Digital Lock Detect Divide By 4

Because the digital lock detect function is based on a phase error, it becomes more difficult to detect a locked condition for larger comparison frequencies. When this bit is enabled, it subdivides the RF PLL comparison frequency (it does not apply to the IF comparison frequency) presented to the digital lock detect circuitry by 4. This enables this circuitry to work at higher comparison frequencies. TI recommends that this bit be enabled whenever the comparison frequency exceeds 20 MHz and RF digital lock detect is being used.

8.6.8.2 IF_RST—IF PLL Counter Reset

When this bit is enabled, the IF PLL N and R counters are reset, and the charge pump is put in a Tri-State condition. This feature should be disabled for normal operation.

NOTE

A counter reset is applied whenever the chip is powered up through software or CE pin.

Table 46. IF_RST—IF PLL Counter Reset

IF_RST	IF PLL N AND R COUNTERS	IF PLL CHARGE PUMP
0 (Default)	Normal Operation	Normal Operation
1	Counter Reset	Tri-State

8.6.8.3 RF_RST—RF PLL Counter Reset

When this bit is enabled, the RF PLL N and R counters are reset and the charge pump is put in a Tri-State condition. This feature should be disabled for normal operation. This feature should be disabled for normal operation.

NOTE

A counter reset is applied whenever the chip is powered up through software or CE pin.

Table 47. RF_RST—RF PLL Counter Reset

RF_RST	RF PLL N AND R COUNTERS	RF PLL CHARGE PUMP
0 (Default)	Normal Operation	Normal Operation
1	Counter Reset	Tri-State

8.6.8.4 RF_TRI—RF Charge Pump Tri-State

When this bit is enabled, the RF PLL charge pump is put in a Tri-State condition, but the counters are not reset. This feature is typically disabled for normal operation.

Table 48. RF_TRI—RF Charge Pump Tri-State

RF_TRI	RF PLL N AND R COUNTERS	RF PLL CHARGE PUMP
0 (Default)	Normal Operation	Normal Operation
1	Normal Operation	Tri-State

8.6.8.5 IF_TRI—IF Charge Pump Tri-State

When this bit is enabled, the IF PLL charge pump is put in a Tri-State condition, but the counters are not reset. This feature is typically disabled for normal operation.

Table 49. IF_TRI—IF Charge Pump Tri-State

IF_TRI	IF PLL N AND R COUNTERS	IF PLL CHARGE PUMP
0 (Default)	Normal Operation	Normal Operation
1	Normal Operation	Tri-State