SNOSB31J July   2009  – December 2014 LMX2541

PRODUCTION DATA.  

  1. 1 Features
  2. 2  Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Not Ensured Characteristics
      2. 7.7.2 Output Power in Bypass Mode
      3. 7.7.3 Output Power in Divided Mode
      4. 7.7.4 RFout Output Impedance
        1. 7.7.4.1 OSCin and Fin Sensitivity
  8. 8 Parameter Measurement Information
    1. 8.1 Bench Test Setups
      1. 8.1.1 Charge Pump Current Measurements
      2. 8.1.2 Charge Pump Current Definitions
        1. 8.1.2.1 Charge Pump Current Definitions
        2. 8.1.2.2 Variation of Charge Pump Current Magnitude vs. Charge Pump Voltage
        3. 8.1.2.3 Variation of Charge Pump Current Magnitude vs. Temperature
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  PLL Reference Oscillator Input Pins
      2. 9.3.2  PLL R Divider
      3. 9.3.3  PLL Phase Detector and Charge Pump
      4. 9.3.4  PLL N Divider and Fractional Circuitry
      5. 9.3.5  Partially Integrated Loop Filter
      6. 9.3.6  Low Noise, Fully Integrated VCO
      7. 9.3.7  Programmable VCO Divider
      8. 9.3.8  Programmable RF Output Buffer
      9. 9.3.9  Powerdown Modes
      10. 9.3.10 Fastlock
      11. 9.3.11 Lock Detect
      12. 9.3.12 Current Consumption
      13. 9.3.13 Fractional Spurs
        1. 9.3.13.1 Primary Fractional Spurs
        2. 9.3.13.2 Sub-Fractional Spurs
      14. 9.3.14 Impact of VCO_DIV on Fractional Spurs
      15. 9.3.15 PLL Phase Noise
        1. 9.3.15.1 , LMX2541SQ3740E Raw Phase Noise Measurement Plot Description
        2. 9.3.15.2 , LMX2541SQ2690 System Phase Noise Plot Description
        3. 9.3.15.3 Phase Noise of PLL
      16. 9.3.16 Impact of Modulator Order, Dithering, and Larger Equivalent Fractions on Spurs and Phase Noise
      17. 9.3.17 Modulator Order
      18. 9.3.18 Programmable Output Power with On/Off
      19. 9.3.19 Loop Filter
      20. 9.3.20 Internal VCO Digital Calibration Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 External VCO Mode
      2. 9.4.2 Digital FSK Mode
    5. 9.5 Programming
      1. 9.5.1 General Programming Information
    6. 9.6 Register Maps
      1. 9.6.1 Register R7
        1. 9.6.1.1  Register R13
          1. 9.6.1.1.1 VCO_DIV_OPT[2:0]
        2. 9.6.1.2  Register R12
        3. 9.6.1.3  Register R9
        4. 9.6.1.4  Register R8
          1. 9.6.1.4.1 AC_TEMP_COMP[4:0]
        5. 9.6.1.5  Register R6
          1. 9.6.1.5.1 RFOUT[1:0] - RFout enable pin
          2. 9.6.1.5.2 DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout
        6. 9.6.1.6  Register R5
          1. 9.6.1.6.1 FL_TOC[13:0] -- Time Out Counter for FastLock
          2. 9.6.1.6.2 FL_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
          3. 9.6.1.6.3 FL_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
          4. 9.6.1.6.4 FL_CPG[4:0] -- Charge Pump Current for Fastlock
        7. 9.6.1.7  Register R4
          1. 9.6.1.7.1 OSC_FREQ [7:0] -- OSCin Frequency for VCO Calibration Clocking
          2. 9.6.1.7.2 VCO_DIV[5:0] - VCO Divider
          3. 9.6.1.7.3 R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3
          4. 9.6.1.7.4 R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4
          5. 9.6.1.7.5 C3_LF[3:0] -- Value for C3 in the Internal Loop Filter
          6. 9.6.1.7.6 C4_LF[3:0] -- Value for C4 in the Internal Loop Filter
        8. 9.6.1.8  Register R3
          1. 9.6.1.8.1  MODE[1:0] -- Operational Mode
          2. 9.6.1.8.2  Powerdown -- Powerdown Bit
          3. 9.6.1.8.3  XO - Crystal Oscillator Mode Select
          4. 9.6.1.8.4  CPG[4:0] -- Charge Pump Current
          5. 9.6.1.8.5  MUX[3:0] -- Multiplexed Output for Ftest/LD Pin
          6. 9.6.1.8.6  CPP - Charge Pump Polarity
          7. 9.6.1.8.7  OSC2X-- OSCin Frequency Doubler
          8. 9.6.1.8.8  FDM - Extended Fractional Denominator Mode Enable
          9. 9.6.1.8.9  ORDER[2:0] -- Delta-Sigma Modulator Order
          10. 9.6.1.8.10 DITH[1:0] -- Dithering
          11. 9.6.1.8.11 CPT - Charge Pump TRI-STATE
          12. 9.6.1.8.12 DLOCK[2:0] - Controls for Digital Lock Detect
          13. 9.6.1.8.13 FSK - Frequency Shift Keying
        9. 9.6.1.9  Register R2
          1. 9.6.1.9.1 PLL_DEN[21:0] -- Fractional Denominator
        10. 9.6.1.10 Registers R1 and R0
          1. 9.6.1.10.1 PLL_R[11:0] -- PLL R Divider Value
          2. 9.6.1.10.2 PLL_N[17:0] PLL N Divider Value
          3. 9.6.1.10.3 PLL_NUM[21:0] -- Fractional Numerator
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Determining the Best Frequency Option of the LMX2541 to Use
      2. 10.1.2 RFout Output Power Test Setup
      3. 10.1.3 Phase Noise Measurement Test Setup
        1. 10.1.3.1 PLL Phase Noise Measurement
          1. 10.1.3.1.1 PLL Phase Noise Measurement - 1/f Noise
          2. 10.1.3.1.2 PLL Phase Noise Measurement - Flat Noise
        2. 10.1.3.2 VCO Phase Noise Measurement
        3. 10.1.3.3 Divider Phase Noise Measurement
      4. 10.1.4 Input and Output Impedance Test Setup
        1. 10.1.4.1 OSCin Input Impedance Measurement
        2. 10.1.4.2 ExtVCOin Input Impedance Measurement
        3. 10.1.4.3 RFout Output Impedance Measurement
      5. 10.1.5 ExtVCOin (NOT OSCin) Input Sensitivity Test Setup
      6. 10.1.6 OSCin Input Sensitivity Test Setup
        1. 10.1.6.1 Input Sensitivity Test Procedure
        2. 10.1.6.2 OSCin Slew Rate Tests
      7. 10.1.7 Typical Connections
        1. 10.1.7.1 Full Chip Mode, Differential OSCin
        2. 10.1.7.2 External VCO Mode, Single-Ended OSCin, RFout Pin not Used
        3. 10.1.7.3 OSCin/OSCin* Connections
          1. 10.1.7.3.1 Single-Ended Operation
          2. 10.1.7.3.2 Differential Operation
          3. 10.1.7.3.3 Crystal Mode Operation
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Configuring the LMX2541 for Optimal Performance
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

12 Layout

12.1 Layout Guidelines

12.1.1 Configuring the LMX2541 for Optimal Performance

  1. Determine the Channel Spacing (fCH)
    • For a system that has a VCO that tunes over several frequencies, the channel spacing is the tuning increment. In the case that the VCO frequency is fixed, this channel spacing is the greatest number that divides both the VCO frequency and the OSCin frequency.
  2. Determine OSCin Frequency (fOSCin)
    • If the OSCin frequency is not already determined, then there are several considerations. A higher frequency is generally, but not always, preferable. One reason for this is that it has a higher slew rate if it is a sine wave. Another reason is that the clock for the VCO frequency calibration is based on the OSCin frequency and in general will run faster for higher OSCin frequencies.
    • Although a higher OSCin frequency is desirable, there are also reasons to use a lower frequency. If the OSCin frequency is strategically chosen, the worst case fractional spur channels might fall out of band. Also, if the OSCin frequency can be chosen such that the fractional denominator can avoid factors of 2 and/or 3, the sub-fractional spurs can be reduced.
  3. Determine the Phase Detector Frequency (fPD) , Charge Pump Gain (KPD) and Fractional Denominator (FDEN)
    • In general, choose the highest phase detector frequency and charge pump gain, unless it leads to loop filter capacitor values that are unrealistically large for a given loop bandwidth. In this case, reducing either the phase detector frequency or the charge pump gain can yield more feasible capacitor values. Other reasons for not using the highest charge pump gain is to allow some adjustment margin to compensate for changes in the VCO gain or allow the use of Fastlock.
    • For choosing the fractional denominator, start with FDEN = fPD/fCH. As discussed previously, there might be reasons to choose larger equivalent fractions.
  4. Design the Loop Filter
  5. Determine the Modulator Order
  6. Determine Dithering and Potential Larger Equivalent Fractional Value

12.2 Layout Example

LMX2541 ta_BoardLayout.pngFigure 35. Layout