JAJSFI5 May 2018 LMX2572LP
PRODUCTION DATA.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | FSK_EN | 0 | FSK_I2S_FS_POL | FSK_I2S_CLK_POL | FSK_SPI_LEVEL | FSK_SPI_DEV_SEL | FSK_MODE_SEL | ||||
R/W-Fh | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 - 11 | R/W | Fh | Program Fh to this field. | |
10 | FSK_EN | R/W | 0h | Enables all FSK modes.
0: Disabled 1: Enabled |
9 | R/W | 0h | Program 0h to this filed. | |
8 | FSK_I2S_FS_POL | R/W | 0h | Sets the polarity of the I2S Frame Sync input in FSK I2S mode.
0: Active HIGH 1: Active LOW |
7 | FSK_I2S_CLK_POL | R/W | 0h | Sets the polarity of the I2S CLK input in FSK I2S mode.
0: Rising edge 1: Falling edge |
6 - 5 | FSK_SPI_LEVEL | R/W | 0h | Defines the desired FSK level in FSK SPI mode. When this bit is zero, FSK operation in this mode is disabled even if FSK_EN = 1.
0: Disabled 1: 2FSK 2: 4FSK 3: 8FSK |
4 - 2 | FSK_SPI_DEV_SEL | R/W | 0h | In FSK SPI mode, these bits select one of the FSK deviations as defined in registers R116 - R123.
0: FSK_DEV0 1: FSK_DEV1 ····· 7: FSK_DEV7 |
1 - 0 | FSK_MODE_SEL | R/W | 0h | Defines FSK mode.
0: Not used 1: FSK I2S 2: FSK SPI 3: FSK SPI FAST |