JAJSM75G December   2015  – August 2022 LMX2592

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  VCO Doubler
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Distribution
      10. 7.3.10 Output Buffer
      11. 7.3.11 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2592 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHA|40
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-9FD2A8ED-4516-421B-B3C4-42B734A9167A-low.gifFigure 5-1 RHA Package40-Pin VQFNTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
CE 1 Input Chip Enable input. Active high powers on the device.
CPout 12 Output Charge pump output. Recommend connecting C1 of loop filter close to pin.
CSB 24 Input SPI chip select bar or uWire latch enable (abbreviated as LE in Figure 6-1). High impedance CMOS input. 1.8 to 3.3-V logic.
DAP GND Ground RFout ground.
GND 2, 4, 6, 13, 14, 25, 31, 34, 39, 40 Ground VCO ground.
MUXout 20 Output Programmable with register MUXOUT_SEL to be readback SDO or lock detect indicator (active high).
NC 5, 28, 30, 32 — Not connected.
OSCinP 8 Input Differential reference input clock (+). High input impedance. Requires connecting series capacitor (0.1-µF recommended).
OSCinM 9 Input Differential reference input clock (–). High input impedance. Requires connecting series capacitor (0.1-µF recommended).
RFoutAM 22 Output Differential output A (–). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
RFoutAP 23 Output Differential output A (+). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
RFoutBP 19 Output Differential output B (+). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
RFoutBM 18 Output Differential output B (–). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
SCK 16 Input SPI or uWire clock (abbreviated as CLK in Figure 6-1). High impedance CMOS input. 1.8 to 3.3-V logic.
SDI 17 Input SPI or uWire data (abbreviated as DATA in Figure 6-1). High impedance CMOS input. 1.8 to 3.3-V logic.
VbiasVARAC 33 Bypass VCO varactor internal voltage, access for bypass. Requires connecting 10-µF capacitor to VCO ground.
VbiasVCO 3 Bypass VCO bias internal voltage, access for bypass. Requires connecting 10-µF capacitor to VCO ground. Place close to pin.
VbiasVCO2 27 Bypass VCO bias internal voltage, access for bypass. Requires connecting 1-µF capacitor to VCO ground.
VCCBUF 21 Supply Output buffer supply. Requires connecting 0.1-µF capacitor to RFout ground.
VCCCP 11 Supply Charge pump supply. Recommend connecting 0.1-µF capacitor to charge pump ground.
VCCDIG 7 Supply Digital supply. Recommend connecting 0.1-µF capacitor to digital ground.
VCCMASH 15 Supply Digital supply. Recommend connecting 0.1-µF and 10-µF capacitor to digital ground.
VCCVCO 37 Supply VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
VCCVCO2 26 Supply VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to VCO ground.
VrefVCO 36 Bypass VCO supply internal voltage, access for bypass. Requires connecting 10-µF capacitor to ground.
VrefVCO2 29 Bypass VCO supply internal voltage, access for bypass. Requires connecting 10-µF capacitor to VCO ground.
VregIN 10 Bypass Input reference path internal voltage, access for bypass. Requires connecting 1-µF capacitor to ground. Place close to pin.
VregVCO 38 Bypass VCO supply internal voltage, access for bypass. Requires connecting 1-µF capacitor to ground.
Vtune 35 Input VCO tuning voltage input. This signal should be kept away from noise sources. Connect a 3.3-nF or more capacitor to VCO ground.