JAJSDN8C March   2017  – April 2019 LMX2594

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Reference Oscillator Input
      2. 8.3.2  Reference Path
        1. 8.3.2.1 OSCin Doubler (OSC_2X)
        2. 8.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 8.3.2.3 Programmable Multiplier (MULT)
        4. 8.3.2.4 Post-R Divider (PLL_R)
        5. 8.3.2.5 State Machine Clock
      3. 8.3.3  PLL Phase Detector and Charge Pump
      4. 8.3.4  N-Divider and Fractional Circuitry
      5. 8.3.5  MUXout Pin
        1. 8.3.5.1 Lock Detect
        2. 8.3.5.2 Readback
      6. 8.3.6  VCO (Voltage-Controlled Oscillator)
        1. 8.3.6.1 VCO Calibration
        2. 8.3.6.2 Determining the VCO Gain
      7. 8.3.7  Channel Divider
      8. 8.3.8  Output Buffer
      9. 8.3.9  Power-Down Modes
      10. 8.3.10 Phase Synchronization
        1. 8.3.10.1 General Concept
        2. 8.3.10.2 Categories of Applications for SYNC
        3. 8.3.10.3 Procedure for Using SYNC
        4. 8.3.10.4 SYNC Input Pin
      11. 8.3.11 Phase Adjust
      12. 8.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
      13. 8.3.13 Ramping Function
        1. 8.3.13.1 Manual Pin Ramping
          1. 8.3.13.1.1 Manual Pin Ramping Example
        2. 8.3.13.2 Automatic Ramping
          1. 8.3.13.2.1 Automatic Ramping Example (Triangle Wave)
      14. 8.3.14 SYSREF
        1. 8.3.14.1 Programmable Fields
        2. 8.3.14.2 Input and Output Pin Formats
          1. 8.3.14.2.1 Input Format for SYNC and SysRefReq Pins
          2. 8.3.14.2.2 SYSREF Output Format
        3. 8.3.14.3 Examples
        4. 8.3.14.4 SYSREF Procedure
      15. 8.3.15 SysRefReq Pin
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Recommended Initial Power-Up Sequence
      2. 8.5.2 Recommended Sequence for Changing Frequencies
      3. 8.5.3 General Programming Requirements
    6. 8.6 Register Maps
      1. 8.6.1  General Registers R0, R1, & R7
        1. Table 24. Field Descriptions
      2. 8.6.2  Input Path Registers
        1. Table 25. Field Descriptions
      3. 8.6.3  Charge Pump Registers (R13, R14)
        1. Table 26. Field Descriptions
      4. 8.6.4  VCO Calibration Registers
        1. Table 27. Field Descriptions
      5. 8.6.5  N Divider, MASH, and Output Registers
        1. Table 28. Field Descriptions
      6. 8.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 29. Field Descriptions
      7. 8.6.7  Lock Detect Registers
        1. Table 30. Field Descriptions
      8. 8.6.8  MASH_RESET
        1. Table 31. Field Descriptions
      9. 8.6.9  SysREF Registers
        1. Table 32. Field Descriptions
      10. 8.6.10 CHANNEL Divider Registers
        1. Table 33. Field Descriptions
      11. 8.6.11 Ramping and Calibration Fields
        1. Table 34. Field Descriptions
      12. 8.6.12 Ramping Registers
        1. 8.6.12.1 Ramp Limits
          1. Table 35. Field Descriptions
        2. 8.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 36. Field Descriptions
        3. 8.6.12.3 Ramping Configuration
          1. Table 37. Field Descriptions
      13. 8.6.13 Readback Registers
        1. Table 38. Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 OSCin Configuration
      2. 9.1.2 OSCin Slew Rate
      3. 9.1.3 RF Output Buffer Power Control
      4. 9.1.4 RF Output Buffer Pullup
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ +85°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VCC Supply voltage 3.15 3.3 3.45 V
ICC Supply current OUTA_PD = 0, OUTB_PD = 1
OUTA_MUX = OUTB_MUX = 1
OUTA_PWR = 31, CPG=7
fOSC= fPD = 100 MHz, fVCO = fOUT = 14 GHz
pOUT = 3 dBm with 50-Ω resistor pullup		 340 mA
Power-on reset current RESET=1 170
Power-down current POWERDOWN=1 5
OUTPUT CHARACTERISTICS
pOUT Single-ended output power(3)(5) 50-Ω resistor pullup
OUTx_PWR = 50 		fOUT = 8 GHz 5 dBm
fOUT = 15 GHz 2
1-nH inductor pullup
OUTx_PWR = 50		 fOUT = 8 GHz 10
fOUT = 15 GHz 7
Xtalk Isolation between outputs A and B. Measured on output A OUTA_MUX = VCO
OUTB_MUX = channel divider		 –50 dBc
H2 Second harmonic(5) OUTA_MUX = VCO
fVCO = 8 GHz		 –20 dBc
OUTA_MUX = VCO
fVCO = 11 GHz		 –30
H3 Third harmonic(5) OUTA_MUX = VCO
fVCO = 8 GHz		 –50 dBc
INPUT SIGNAL PATH
fOSCin Reference input frequency OSC_2X = 0 5 1400 MHz
OSC_2X = 1 5 200
vOSCin Reference input voltage AC-coupled required (2) 0.2 2 Vpp
fMULT Multiplier frequency (only applies when multiplier is enabled) Input range 30 70 MHz
Output range 180 250
PHASE DETECTOR AND CHARGE PUMP
fPD Phase detector frequency(2) Integer mode MASH_ORDER = 0 0.125 400 MHz
Fractional mode MASH_ORDER= 1, 2, 3 5 300
MASH_ORDER = 4 5 240
ICPout Charge-pump leakage current CPG = 0 15 nA
Effective charge pump current. This is the sum of the up and down currents CPG = 4 3 mA
CPG = 1 6
CPG = 5 9
CPG = 3 12
CPG = 7 15
PNPLL_1/f Normalized PLL 1/f noise fPD = 100 MHz, fVCO = 12 GHz(4)(4)(4)(4) –129 dBc/Hz
PNPLL_flat Normalized PLL noise floor –236 dBc/Hz
VCO CHARACTERISTICS
PNVCO VCO phase noise VCO1
fVCO = 8 GHz		 10 kHz –80 dBc/Hz
100 kHz –107
1 MHz –128
10 MHz –148
90 MHz –157
VCO2
fVCO = 9.2 GHz		 10 kHz –79
100 kHz –105
1 MHz –127
10 MHz –147
90 MHz –157
VCO3
fVCO = 10.3 GHz		 10 kHz –77
100 kHz –104
1 MHz –126
10 MHz –147
90 MHz –157
VCO4
fVCO = 11.3 GHz		 10 kHz –76
100 kHz –103
1 MHz –125
10 MHz –145
90 MHz –158
VCO5
fVCO = 12.5 GHz		 10 kHz –74
100 kHz –100
1 MHz –123
10 MHz –144
90 MHz –157
VCO6
fVCO = 13.3 GHz		 10 kHz –73
100 kHz –100
1 MHz –122
10 MHz –143
90 MHz –155
VCO7
fVCO = 14.5 GHz		 10 kHz –73
100 kHz –99
1 MHz –121
10 MHz –143
90 MHz –152
tVCOCAL VCO calibration speed Switch across the entire frequency band
fOSC = 200 MHz, fPD = 100 MHz(1) 		No assist 50 µs
Partial assist 35
Close frequency 20
Full assist 5
KVCO VCO gain 8 GHz 92 MHz/V
9.2 GHz 91
10.3 GHz 115
11.3 GHz 121
12.5 GHz 195
13.3 GHz 190
14.5 GHz 213
|ΔTCL| Allowable temperature drift when VCO is not recalibrated RAMP_EN = 0 or RAMP_MANUAL= 1 125 °C
H2 VCO second harmonic fVCO = 8 GHz, divider disabled –20 dBc
H3 VCO third haromonic fVCO = 8 GHz, divider disabled –50
SYNC PIN AND PHASE ALIGNMENT
fOSCinSYNC Maximum usable OSCin with sync pin (Figure 27) Category 3 0 100 MHz
Categories1 and 2 0 1400
DIGITAL INTERFACE
Applies to SLK, SDI, CSB, CE, RampDir, RampClk, MUXout, SYNC (CMOS Mode), SysRefReq (CMOS Mode)
VIH High-level input voltage 1.4 Vcc V
VIL Low-level input voltage 0 0.4 V
IIH High-level input current –25 25 µA
IIL Low-level input current –25 25 µA
VOH High-level output voltage MUXout pin Load current = –10 mA VCC – 0.4 V
VOL Low-level output voltage Load current = 10 mA 0.4 V
(1) See Application and Implementation for more details on the different VCO calibration modes.
(2) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.
(3) Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port terminated to 50 ohm load.
(4) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10 PLL_Flat / 10 + 10 PLL_flicker / 10 )
(5) Output power, spurs, and harmonics can vary based on board layout and components.