7.6.1.21 R44 Register (Address = 0x2C) [reset = 0x1FA3]
R44 is shown in Figure 51 and described in Table 42.
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Figure 51. R44 Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
OUTA_PWR |
R-0x0 |
R/W-0x1F |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
OUTB_PD |
OUTA_PD |
MASH_RESET_N |
RESERVED |
MASH_ORDER |
R/W-0x1 |
R/W-0x0 |
R/W-0x1 |
R-0x0 |
R/W-0x3 |
|
Table 42. R44 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-14 |
RESERVED |
R |
0x0 |
|
13-8 |
OUTA_PWR |
R/W |
0x1F |
Sets current that controls output power for output A. 0 is minimum current, 63 is maximum current. |
7 |
OUTB_PD |
R/W |
0x1 |
\nPowers down output B |
6 |
OUTA_PD |
R/W |
0x0 |
Powers down output A |
5 |
MASH_RESET_N |
R/W |
0x1 |
Active low reset for MASH |
4-3 |
RESERVED |
R |
0x0 |
|
2-0 |
MASH_ORDER |
R/W |
0x3 |
MASH Order |