JAJSF07A
March 2018 – November 2018
LMX8410L
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
ブロック概略図
4
改訂履歴
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Device Configurations and Feature Description
7.3.1.1
RF, LO and IF Interfaces
7.3.1.1.1
RF Interface
7.3.1.1.2
LO Interface
7.3.1.1.2.1
LO Interface as Output Port
7.3.1.1.2.2
LO Interface as Input Port
7.3.1.1.3
Baseband Interface
7.3.1.2
Device Configurations Overview
7.3.1.2.1
Initialize the Device
7.3.1.2.2
Configure LO Modes
7.3.1.2.3
Set Up External LO Clock
7.3.1.2.4
Perform DCOC (DC Offset Correction)
7.3.1.2.5
Turn Off SM Clock
7.3.1.2.6
Perform IMRR (Image Rejection Ratio) Calibration
7.3.1.3
State Machine Clock
7.3.1.3.1
Set Divider Values For Internal LO Mode
7.3.1.3.2
Set Divider Values For External LO Mode
7.3.1.4
DCOC (DC Offset Correction)
7.3.1.4.1
RF Input Power Restriction During DCOC
7.3.1.4.2
Set Up DCOC Clock Divider
7.3.1.5
Image Rejection Calibration
7.3.1.5.1
Phase Calibration
7.3.1.5.2
Gain Calibration
7.3.1.6
IF Amplifier Common Mode Configurations
7.3.1.7
Synchronization Mode (Internal LO Mode Only)
7.3.1.7.1
Synchronization of the LO_OUT Output to the Fosc Input
7.3.1.7.2
Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO
7.4
Device Functional Modes
7.4.1
Internal LO Mode
7.4.1.1
VCO Range Uncertainty for 7.5 to 7.7 GHz
7.4.2
External LO Mode
7.5
Programming
7.5.1
General Comments Regarding Programming
7.5.2
Recommended Initial Power Up Sequence
7.5.3
Recommended and Power on Reset Bit Values
7.6
Register Map
7.6.1
R0 Register (Address = 0x0) [reset = X]
Table 9.
R0 Register Field Descriptions
7.6.2
R1 Register (Address = 0x1) [reset = 0x3]
Table 10.
R1 Register Field Descriptions
7.6.3
R2 Register (Address = 0x2) [reset = X]
Table 11.
R2 Register Field Descriptions
7.6.4
R9 Register (Address = 0x9) [reset = X]
Table 12.
R9 Register Field Descriptions
7.6.5
R10 Register (Address = 0xA) [reset = 0x80]
Table 13.
R10 Register Field Descriptions
7.6.6
R11 Register (Address = 0xB) [reset = 0x10]
Table 14.
R11 Register Field Descriptions
7.6.7
R14 Register (Address = 0xE) [reset = 0x70]
Table 15.
R14 Register Field Descriptions
7.6.8
R36 Register (Address = 0x24) [reset = 0x64]
Table 16.
R36 Register Field Descriptions
7.6.9
R37 Register (Address = 0x25) [reset = 0x200]
Table 17.
R37 Register Field Descriptions
7.6.10
R38 Register (Address = 0x26) [reset = 0x0]
Table 18.
R38 Register Field Descriptions
7.6.11
R39 Register (Address = 0x27) [reset = 0x2710]
Table 19.
R39 Register Field Descriptions
7.6.12
R40 Register (Address = 0x28) [reset = 0x0]
Table 20.
R40 Register Field Descriptions
7.6.13
R41 Register (Address = 0x29) [reset = 0x0]
Table 21.
R41 Register Field Descriptions
7.6.14
R42 Register (Address = 0x2A) [reset = 0x0]
Table 22.
R42 Register Field Descriptions
7.6.15
R43 Register (Address = 0x2B) [reset = 0x0]
Table 23.
R43 Register Field Descriptions
7.6.16
R44 Register (Address = 0x2C) [reset = 0xA2]
Table 24.
R44 Register Field Descriptions
7.6.17
R46 Register (Address = 0x2E) [reset = 0x1]
Table 25.
R46 Register Field Descriptions
7.6.18
R58 Register (Address = 0x3A) [reset = 0x8000]
Table 26.
R58 Register Field Descriptions
7.6.19
R59 Register (Address = 0x3B) [reset = 0x1]
Table 27.
R59 Register Field Descriptions
7.6.20
R69 Register (Address = 0x45) [reset = 0x0]
Table 28.
R69 Register Field Descriptions
7.6.21
R70 Register (Address = 0x46) [reset = 0xC350]
Table 29.
R70 Register Field Descriptions
7.6.22
R75 Register (Address = 0x4B) [reset = 0x0]
Table 30.
R75 Register Field Descriptions
7.6.23
R78 Register (Address = 0x4E) [reset = 0x0]
Table 31.
R78 Register Field Descriptions
7.6.24
R79 Register (Address = 0x4F) [reset = 0x7000]
Table 32.
R79 Register Field Descriptions
7.6.25
R80 Register (Address = 0x50) [reset = 0xA]
Table 33.
R80 Register Field Descriptions
7.6.26
R81 Register (Address = 0x51) [reset = 0x0]
Table 34.
R81 Register Field Descriptions
7.6.27
R82 Register (Address = 0x52) [reset = 0x23]
Table 35.
R82 Register Field Descriptions
7.6.28
R83 Register (Address = 0x53) [reset = 0x2000]
Table 36.
R83 Register Field Descriptions
7.6.29
R84 Register (Address = 0x54) [reset = 0x1900]
Table 37.
R84 Register Field Descriptions
7.6.30
R88 Register (Address = 0x58) [reset = 0x0]
Table 38.
R88 Register Field Descriptions
7.6.31
R94 Register (Address = 0x5E) [reset = 0x8080]
Table 39.
R94 Register Field Descriptions
7.6.32
R95 Register (Address = 0x5F) [reset = X]
Table 40.
R95 Register Field Descriptions
7.6.33
R103 Register (Address = 0x67) [reset = X]
Table 41.
R103 Register Field Descriptions
7.6.34
R110 Register (Address = 0x6E) [reset = X]
Table 42.
R110 Register Field Descriptions
7.6.35
R111 Register (Address = 0x6F) [reset = 0x0]
Table 43.
R111 Register Field Descriptions
7.6.36
R112 Register (Address = 0x70) [reset = 0x0]
Table 44.
R112 Register Field Descriptions
7.6.37
R121 Register (Address = 0x79) [reset = 0x0]
Table 45.
R121 Register Field Descriptions
7.6.38
R123 Register (Address = 0x7B) [reset = 0x3]
Table 46.
R123 Register Field Descriptions
7.6.39
R126 Register (Address = 0x7E) [reset = X]
Table 47.
R126 Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.1.1
High Frequency Trace Routing
10.1.2
Power Trace Routing
10.2
Layout Examples
11
デバイスおよびドキュメントのサポート
11.1
ドキュメントのサポート
11.1.1
関連資料
11.2
ドキュメントの更新通知を受け取る方法
11.3
コミュニティ・リソース
11.4
商標
11.5
静電気放電に関する注意事項
11.6
Glossary
12
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGZ|48
MPQF123F
サーマルパッド・メカニカル・データ
RGZ|48
QFND131R
発注情報
jajsf07a_oa
jajsf07a_pm
Device Images
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