7.6.32 R95 Register (Address = 0x5F) [reset = X]
R95 is shown in Figure 83 and described in Table 40.
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Figure 83. R95 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
R-0x0 |
|
Table 40. R95 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15 |
IMRR_PHCAL_POL |
R/W |
X |
IMRR Phase polarity control using the phase interpolar. |
14-9 |
IMRR_PHCAL |
R/W |
X |
IMRR Phase control using the phase interpolar. Preferred method of the IMRR phase correction. |
8 |
LODRV_IMRR_PHCAL_POLCTRL |
R/W |
X |
IMRR Phase polarity control using the slew control driver. |
7-0 |
RESERVED |
R |
0x0 |
|