JAJSFZ2E August   2012  – September 2021 LMZ20501

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Nano Scale Package
      2. 7.3.2 Internal Synchronous Rectifier
      3. 7.3.3 Current Limit Protection
      4. 7.3.4 Start-Up
      5. 7.3.5 Dropout Behavior
      6. 7.3.6 Power Good Flag Function
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Setting The Output Voltage
        3. 8.2.1.3 Output and Feedforward Capacitors
        4. 8.2.1.4 Input Capacitors
        5. 8.2.1.5 Maximum Ambient Temperature
        6. 8.2.1.6 Options
      2. 8.2.2 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Soldering Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

6.6 System Characteristics

The following specifications apply to the circuit found in Figure 8-1 with the appropriate modifications from Table 8-1. These parameters are not tested in production and represent typical performance only. Unless otherwise stated the following conditions apply: TA = 25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Load RegulationPercent output voltage change for the given load current changeVOUT = 1.2 V,
VIN = 5 V, IOUT = 0 A to 1 A, PWM		0.14%
VOUT = 1.8 V
VIN = 5 V, IOUT = 0 A to 1 A, PWM		0.15%
VOUT = 3.3 V
VIN = 5 V, IOUT = 0 A to 1 A, PWM		0.11%
Line RegulationPercent output voltage change for the given change in input voltageVOUT = 1.2 V
IOUT = 1 A, VIN = 3 V to 5 V, PWM		0.16%
VOUT = 1.8 V
IOUT = 1 A, VIN = 3 V to 5 V, PWM		0.12%
VOUT = 3.3 V
IOUT = 1 A,VIN = 4 V to 5 V, PWM		0.1%
VR-PWMOutput voltage ripple in PWMVOUT = 1.2 V
IOUT = 1 A, VIN = 5 V, PWM		3.3mV pk-pk
VOUT = 1.8 V
IOUT = 1 A, VIN = 5 V, PWM		3.3
VOUT = 3.3V
IOUT= 1 A, VIN = 5 V, PWM		4.2
VR-PFMOutput voltage ripple in PFMVOUT = 1.2V
IOUT= 1 mA, VIN = 3 V, PFM		22mV pk-pk
VOUT = 1.8 V
IOUT= 1 mA, VIN=3 V, PFM		22
VOUT = 3.3 V
IOUT = 1 mA, VIN = 5 V, PFM		40
Load TransientOutput voltage deviation from nominal due to a load current stepVOUT = 1.2 V
VIN = 5 V, IOUT = 0 A to 1 A, Tr = Tf = 2 µs, PWM		±60mV
VOUT = 1.8 V
VIN = 5 V, IOUT = 0 A to 1 A, Tr = Tf = 2 µs, PWM		±50
VOUT = 3.3 V
VIN = 5 V, IOUT = 0 A to 1 A, Tr = Tf = 2 µs, PWM		±60
Line TransientOutput voltage deviation due to an input voltage stepVOUT = 1.2V
IOUT = 1 A, VIN = 3 V to 5 V, Tr = Tf = 50 µs, PWM		25mV pk-pk
VOUT = 1.8 V
IOUT = 1 A, VIN = 3 V to 5 V, Tr = Tf = 50 µs, PWM		30
VOUT = 3.3 V
IOUT = 1 A, VIN = 4 V to 5 V, Tr = Tf = 50 µs, PWM		20
ηPeak efficiencyVOUT = 1.2 V
VIN = 3 V		87%
VOUT = 1.8 V
VIN = 3 V		91%
VOUT = 3.3 V
VIN = 4.2 V		94%
Full load efficiencyVOUT = 1.2 V
VIN = 3 V, IOUT = 1 A		83%
VOUT = 1.8 V
VIN = 3 V, IOUT = 1 A		87%
VOUT = 3.3 V
VIN = 4.2 V, IOUT = 1 A		93%