JAJSFZ2E August 2012 – September 2021 LMZ20501
PRODUCTION DATA
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The LMZ20501 is designed to work with low-ESR ceramic capacitors. The effective value of these capacitors is defined as the actual capacitance under voltage bias and temperature. All ceramic capacitors have large voltage coefficients, in addition to normal tolerances and temperature coefficients. Under D.C. bias, the capacitance value drops considerably. Larger case sizes, higher voltage capacitors, or both are better in this regard. To help mitigate these effects, multiple small capacitors can be used in parallel to bring the minimum effective capacitance up to the desired value. This can also ease the RMS current requirements on a single capacitor. Typically, 10-V, X5R, 0805 capacitors are adequate for the output, while 16-V capacitors can be used on the input. Some recommended component values are provided in Table 8-1. Also, shown are the measured values of effective input and output capacitance for the given capacitor. If smaller values of output capacitance are used, CFF must be adjusted to give good phase margin. In any case, load transient response will be compromised with lower values of output capacitance. Values much lower than those found in Table 8-1 should be avoided.
In practice, the output capacitor and CFF are adjusted for the best transient response and highest loop phase margin. Load transient testing and Bode plots are the best way to validate any given design. The Optimizing Transient Response of Internally Compensated DC-DC Converters Application Report should prove helpful when optimizing the feedforward capacitor. Also, the AN-1889 How to Measure the Loop Transfer Function of Power Supplies Application Report details a simple method of creating a Bode plot with basic laboratory equipment. The values of CFF found in Table 8-1 provide a good starting point.
A careful study of the temperature and bias voltage variation of any candidate ceramic capacitor should be made in order to make sure that the minimum values of effective capacitance are provided. The best way to obtain an optimum design is to use the Texas Instruments WEBENCH tool.
The maximum value of total output capacitance should be limited to between 100 µF and 200 µF. Large values of output capacitance can prevent the regulator from starting-up correctly and adversely affect the loop stability. If values in the range given above, or larger, are to be used, then a careful study of start-up at full load and loop stability must be performed.