JAJSG01D June   2012  – August 2018 LMZ20502

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      VOUT = 1.8V、自動モードでの標準的な効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Nano Scale Package
      2. 7.3.2 Internal Synchronous Rectifier
      3. 7.3.3 Current Limit Protection
      4. 7.3.4 Start-Up
      5. 7.3.5 Dropout Behavior
      6. 7.3.6 Power Good Flag Function
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 PFM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Custom Design With WEBENCH® Tools
        2. 8.2.1.2 Setting The Output Voltage
        3. 8.2.1.3 Output and Feed-Forward Capacitors
        4. 8.2.1.4 Input Capacitors
        5. 8.2.1.5 Maximum Ambient Temperature
        6. 8.2.1.6 Options
      2. 8.2.2 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Soldering Information
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 WEBENCH®ツールによるカスタム設計
      3. 11.1.3 ドキュメントのサポート
        1. 11.1.3.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIL|8
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature range of –40°C to 125°C, unless otherwise noted. Minimum and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 3.6 V
PARAMETER TEST CONDITIONS MIN(1) TYP MAX(1) UNIT
VFB Feedback voltage VIN = 3.6 V 0.594 0.6 0.606 V
IQ_AUTO Operating quiescent current in AUTO mode AUTO mode, VFB = 0.8V 72 90 µA
IQ_PWM Operating quiescent current in forced PWM mode PWM mode, VFB = 0.8V 490 620 µA
IQ_off Shutdown quiescent current(2) VIN = 3.6 V, VEN = 0.0 V 0.7 1.5 µA
VIN = 5.5 V, VEN = 0.0 V 1.0 2.4
VUVLO Input supply under-voltage lock-out thresholds Rising 2.5 V
Falling 2.3
VEN High Level Input Voltage VIH 1.4 V
Low Level Input Voltage VIL 0.4
VMODE High Level Input Voltage VIH 1.2 V
Low Level Input Voltage VIL 0.4
I LIM Peak switch current limit(3) 2.1 2.7 A
Fosc Internal oscillator frequency 2.5 3.0 3.2 MHz
TON Minimum switch on-time(5) 50 ns
Tss Soft start time(5) 800 µs
RPG Power good flag pull-down Rdson 40 70 110 Ω
VPG1 Power good flag, under-voltage trip(4) % of feedback voltage, rising 92%
VPG2 Power good flag, under-voltage trip(4) % of feedback voltage, falling 88%
VPG3 Power good flag, over-voltage trip(4) % of feedback voltage, rising 112%
VPG4 Power good flag, over-voltage trip(4) % of feedback voltage, falling 108%
TSD Thermal shutdown(5) Rising threshold 159 °C
Thermal shutdown hysteresis(5) 15 °C
(1) MIN and MAX limits are 100% production tested at 25°C. Limits over the operating temperature range are verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Shutdown current includes leakage current of the switching transistors.
(3) This is the peak switch current limit measured with a slow current ramp. Due to inherent delays in the current limit comparator, the peak current limit measured at 3MHz will be larger.
(4) See Power Good Flag Function for explanation of voltage levels.
(5) This parameter is not tested in production.