JAJSG02D August   2012  – August 2018 LMZ21700

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      VIN = 12Vでの効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1. Table 1. Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Package Construction
    4. 7.4 Feature Description
      1. 7.4.1 Input Under Voltage Lockout
      2. 7.4.2 Enable Input (EN)
      3. 7.4.3 Softstart and Tracking Function (SS)
      4. 7.4.4 Power Good Function (PG)
      5. 7.4.5 Output Voltage Setting
      6. 7.4.6 Output Current Limit and Output Short Circuit Protection
      7. 7.4.7 Thermal Protection
    5. 7.5 Device Functional Modes
      1. 7.5.1 PWM Mode Operation
      2. 7.5.2 PSM Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor (CIN)
        2. 8.2.2.2 Output Capacitor (COUT)
        3. 8.2.2.3 Softstart Capacitor (CSS)
        4. 8.2.2.4 Power Good Resistor (RPG)
        5. 8.2.2.5 Feedback Resistors (RFBB and RFBT)
      3. 8.2.3 Application Curves
        1. 8.2.3.1 VOUT = 1.2 V
        2. 8.2.3.2 VOUT = 1.8 V
        3. 8.2.3.3 VOUT = 2.5 V
        4. 8.2.3.4 VOUT = 3.3 V
        5. 8.2.3.5 VOUT = 5.0 V
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
    1. 9.1 Voltage Range
    2. 9.2 Current Capability
    3. 9.3 Input Connection
      1. 9.3.1 Voltage Drops
      2. 9.3.2 Stability
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Minimize the High di/dt Loop Area
      2. 10.1.2 Protect the Sensitive Nodes in the Circuit
      3. 10.1.3 Provide Thermal Path and Shielding
    2. 10.2 Layout Example
      1. 10.2.1 High Density Layout Example for Space Constrained Applications
        1. 10.2.1.1 35 mm² Solution Size (Single Sided)
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
    2. 11.2 開発サポート
      1. 11.2.1 WEBENCH®ツールによるカスタム設計
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Tape and Reel Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • SIL|8
サーマルパッド・メカニカル・データ
発注情報

8.2.2.1 Input Capacitor (CIN)

Low ESR multi-layer ceramic capacitors (MLCC) are recommended for the input capacitor of the LMZ21700. Using a ≥ 10 µF ceramic input capacitor in ≥ 0805 (2012 metric) case size with 25 V rating typically provides sufficient VIN bypass. Use of multiple capacitors can also be considered. Ceramic capacitors with X5R and X7R temperature characteristics are recommended. These provide an optimal balance between small size, cost, reliability, and performance for applications with limited space. The DC voltage bias characteristics of the capacitors must be considered when selecting the DC voltage rating and case size of these components. The effective capacitance of an MLCC is typically reduced by the DC voltage bias applied across its terminals. Selecting a part with larger capacitance, larger case size, or higher voltage rating can compensate for the capacitance loss due to the DC voltage bias effect. For example, a 10 µF, X7R, 25 V rated capacitor used under 12 V DC bias may have approximately 8 µF effective capacitance in a 1210 (3225 metric) case size and about 6 µF in a 1206 (3216 metric) case size. As another example, a 10 µF, X7R, 16 V rated capacitor in a 1210 (3225 metric) case size used at 12 V DC bias may have approximately 5.5 µF effective capacitance. Check the capacitor specifications published by the manufacturer.