JAJSBA0Q January   2000  – December 2017 LP2950-N , LP2951-N

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     LP2951の概略回路図
  3. 3 概要
    1.     LP2950-Nの概略回路図
  4. 4 改訂履歴
  5. 5 Voltage Options
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: LP2950-N
    2.     Pin Functions: LP2951-N
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: LP2950-N
    5. 7.5 Thermal Information: LP2951-N
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Fixed Voltage Options and Programmable Voltage Version
      2. 8.3.2 High Accuracy Output Voltage
      3. 8.3.3 Low Dropout Voltage
      4. 8.3.4 Shutdown Mode
      5. 8.3.5 Error Detection Comparator Output
      6. 8.3.6 Internal Protection Circuitry
        1. 8.3.6.1 Short-Circuit Protection (Current Limit)
        2. 8.3.6.2 Thermal Protection
      7. 8.3.7 Enhanced Stability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with 30 V ≥ VIN > VOUT(TARGET) + 1 V
      2. 8.4.2 Operation with Shutdown Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1  1-A Regulator with 1.2-V Dropout
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Capacitor Requirements
          2. 9.2.1.2.2 Input Capacitor Requirements
          3. 9.2.1.2.3 Error Detection Comparator Output
          4. 9.2.1.2.4 Programming the Output Voltage (LP2951-N)
          5. 9.2.1.2.5 Reducing Output Noise
        3. 9.2.1.3 Application Curves
      2. 9.2.2  300-mA Regulator with 0.75-V Dropout
      3. 9.2.3  Wide Input Voltage Range Current Limiter
      4. 9.2.4  Low Drift Current Source
      5. 9.2.5  5-V Current Limiter
      6. 9.2.6  Regulator with Early Warning and Auxiliary Output
      7. 9.2.7  Latch Off When Error Flag Occurs
      8. 9.2.8  2-A Low Dropout Regulator
      9. 9.2.9  5-V Regulator with 2.5-V Sleep Function
      10. 9.2.10 Open Circuit Detector for 4 → 20-mA Current Loop
      11. 9.2.11 Regulator with State-of-Charge Indicator
      12. 9.2.12 Low Battery Disconnect
      13. 9.2.13 System Overtemperature Protection Circuit
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 WSON Mounting
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Thermal Information: LP2951-N

THERMAL METRIC(1) LP2951-N UNIT
P (PDIP) D (SOIC) DGK (VSSOP) NGT (WSON)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA(2) Junction-to-ambient thermal resistance, High K 56.3 117.7 171.0 43.3(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.7 63.7 62.3 35.0 °C/W
RθJB Junction-to-board thermal resistance 33.5 57.9 91.4 23.3 °C/W
ψJT Junction-to-top characterization parameter 22.9 15.9 8.9 0.5 °C/W
ψJB Junction-to-board characterization parameter 33.3 57.5 90.1 20.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a 9.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Thermal resistance value RθJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(3) The PCB for the WSON (NGT) package RθJA includes six (6) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.