JAJS821Q April   2000  – November 2023 LP2980-N

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
        1. 7.1.1.1 Recommended Capacitors for the Legacy Chip
        2. 7.1.1.2 Recommended Capacitors for the New Chip
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
      5. 7.1.5 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/OFF Input Operation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 Device Nomenclature
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
∆VOUT Output voltage tolerance IL = 1mA Legacy chip (standard grade) −1.0 1.0 %
Legacy chip (A grade) −0.5 0.5
New chip −0.5 0.5
1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) −1.5 1.5
Legacy chip (A grade) −0.75 0.75
New chip −0.5 0.5
1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) −3.5 3.5
Legacy chip (A grade) −2.5 2.5
New chip −1.0 1.0
ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V
New chip 0.002 0.014
VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032
New chip 0.002 0.032
VIN - VOUT Dropout voltage(1) IOUT = 0 mA Legacy chip 1 3 mV
New chip 1 2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5
New chip 3
IOUT = 1 mA Legacy chip 7 10
New chip 11.5 14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15
New chip 17
IOUT = 10 mA Legacy chip 40 60
New chip 98 115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 90
New chip 148
IOUT = 50 mA Legacy chip 120 150
New chip 120 145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 225
New chip 184
IGND GND pin current IOUT = 0 mA Legacy chip 65 95 uA
New chip 69 95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 65 125
New chip 120
IOUT = 1 mA Legacy chip 75 110
New chip 78 110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170
New chip 140
IOUT = 10 mA Legacy chip 120 220
New chip 175 210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 400
New chip 250
IOUT = 50 mA Legacy chip 350 600
New chip 380 440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 900
New chip 650
VON/OFF < 0.18 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0 1
New chip 1.12 2.25
VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V
VUVLO- Falling bias supply UVLO VIN falling,  –40°C ≤ TJ ≤ 125°C 1.9 2.07
VUVLO(HYST) UVLO hysteresis  –40°C ≤ TJ ≤ 125°C 0.130
IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 150 mA
New chip 150
IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 110 150
New chip 110 150
VON/OFF ON/OFF input voltage Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.55 0.18 V
New chip 0.15
High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 1.4
New chip 1.6
ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V,–40°C ≤ TJ ≤ 125°C Legacy chip 0 -1 uA
New chip -0.9
VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 5 15
New chip 2.20
ΔVO/ΔVIN Ripple rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB
f = 1 kHz, COUT = 10 µF New chip 75
f = 100 kHz, ILOAD = 50mA New chip 45
Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 10uF, VOUT = 3.3V, ILOAD = 50mA Legacy chip 160 µVRMS
Bandwidth = 300 Hz to 50 kHz, COUT = 2.2uF, VOUT = 3.3V, ILOAD = 50mA New chip 140
Bandwidth = 10 Hz to 100 kHz, COUT = 2.2uF, VOUT = 3.3V, ILOAD = 50mA New chip 50
Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C
Tsd- Reset, temperature decreasing 150
(1) Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) - 100mV for fixed output devices.