Input capacitor:

For the legacy chip, an input capacitor (C_IN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground.

For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source.

Output capacitor:

For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-6).

For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the LP2981-N マイクロパワー 100mA 超低ドロップアウト レギュレータ、SOT23 パッケージ LP2981-N 100mA、低ドロップアウト レギュレータ、SOT-23 パッケージ LP2981-N 100mA、低ドロップアウト レギュレータ、SOT-23 パッケージ 特長 特長 アプリケーション アプリケーション 概要 概要 Table of Contents Table of Contents Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Electrical Characteristics Electrical Characteristics Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description Output Enable Output Enable Dropout Voltage Dropout Voltage Current Limit Current Limit Undervoltage Lockout (UVLO) Undervoltage Lockout (UVLO) Thermal Shutdown Thermal Shutdown Output Pulldown Output Pulldown Device Functional Modes Device Functional Modes Device Functional Mode Comparison Device Functional Mode Comparison Normal Operation Normal Operation Dropout Operation Dropout Operation Disabled Disabled Application and Implementation Application and Implementation Application Information Application Information Recommended Capacitor Types Recommended Capacitor Types Recommended Capacitors for the Legacy Chip Recommended Capacitors for the Legacy Chip Recommended Capacitors for the New Chip Recommended Capacitors for the New Chip Input and Output Capacitor Requirements Input and Output Capacitor Requirements Estimating Junction Temperature Estimating Junction Temperature Power Dissipation (PD) Power Dissipation (PD) Reverse Current Reverse Current Typical Application Typical Application Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure ON and OFF Input Operation ON and OFF Input Operation Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Example Layout Example Device and Documentation Support Device and Documentation Support Device Nomenclature Device Nomenclature サード・パーティ製品に関する免責事項 サード・パーティ製品に関する免責事項 Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates Related Documentation Related Documentation サポート・リソース サポート・リソース Trademarks Trademarks 静電気放電に関する注意事項 静電気放電に関する注意事項 用語集 用語集 Revision History Revision History Revision History Revision History Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information 重要なお知らせと免責事項 重要なお知らせと免責事項 LP2981-N 100mA、低ドロップアウト レギュレータ、SOT-23 パッケージ LP2981-N 100mA、低ドロップアウト レギュレータ、SOT-23 パッケージ 特長 O 文書全体にわたって表、図、相互参照の採番方法を更新 yes O 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes O ドキュメントに M3 デバイスを追加 yes 入力電圧 (VIN) 範囲： 従来のチップ：2.1 V ～ 16 V 新しいチップ：2.5V～16V 出力電圧 (VOUT) 範囲：1.2 V ～ 5.0 V 出力電圧 (VOUT) 精度： ±0.75% (A グレードの従来チップ) ±1.25% (標準グレードの従来チップ) ±0.5% (A グレードおよび標準グレードの新チップ) 負荷および温度に対する出力電圧 (VOUT) 精度：±1% (新チップ) 出力電流：最大 100mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：620μA (ILOAD = 100 mA の場合) シャットダウン電流と温度との関係： < 1μA (従来チップ) ≤ 1.75μA (新チップ) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作 (新チップ) 高 PSRR (新チップ)： 1kHz で 75dB、1MHz で 45dB 動作時接合部温度：-40℃～+125℃ パッケージ：5 ピン SOT-23 (DBV) 特長 O 文書全体にわたって表、図、相互参照の採番方法を更新 yes O 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes O ドキュメントに M3 デバイスを追加 yes O 文書全体にわたって表、図、相互参照の採番方法を更新 yes O 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes O ドキュメントに M3 デバイスを追加 yes O 文書全体にわたって表、図、相互参照の採番方法を更新 yes O文書全体にわたって表、図、相互参照の採番方法を更新yes O 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes O現在のファミリのフォーマットに合わせてドキュメント全体を変更yes O ドキュメントに M3 デバイスを追加 yes Oドキュメントに M3 デバイスを追加yes 入力電圧 (VIN) 範囲： 従来のチップ：2.1 V ～ 16 V 新しいチップ：2.5V～16V 出力電圧 (VOUT) 範囲：1.2 V ～ 5.0 V 出力電圧 (VOUT) 精度： ±0.75% (A グレードの従来チップ) ±1.25% (標準グレードの従来チップ) ±0.5% (A グレードおよび標準グレードの新チップ) 負荷および温度に対する出力電圧 (VOUT) 精度：±1% (新チップ) 出力電流：最大 100mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：620μA (ILOAD = 100 mA の場合) シャットダウン電流と温度との関係： < 1μA (従来チップ) ≤ 1.75μA (新チップ) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作 (新チップ) 高 PSRR (新チップ)： 1kHz で 75dB、1MHz で 45dB 動作時接合部温度：-40℃～+125℃ パッケージ：5 ピン SOT-23 (DBV) 入力電圧 (VIN) 範囲： 従来のチップ：2.1 V ～ 16 V 新しいチップ：2.5V～16V 出力電圧 (VOUT) 範囲：1.2 V ～ 5.0 V 出力電圧 (VOUT) 精度： ±0.75% (A グレードの従来チップ) ±1.25% (標準グレードの従来チップ) ±0.5% (A グレードおよび標準グレードの新チップ) 負荷および温度に対する出力電圧 (VOUT) 精度：±1% (新チップ) 出力電流：最大 100mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：620μA (ILOAD = 100 mA の場合) シャットダウン電流と温度との関係： < 1μA (従来チップ) ≤ 1.75μA (新チップ) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作 (新チップ) 高 PSRR (新チップ)： 1kHz で 75dB、1MHz で 45dB 動作時接合部温度：-40℃～+125℃ パッケージ：5 ピン SOT-23 (DBV) 入力電圧 (VIN) 範囲： 従来のチップ：2.1 V ～ 16 V 新しいチップ：2.5V～16V 出力電圧 (VOUT) 範囲：1.2 V ～ 5.0 V 出力電圧 (VOUT) 精度： ±0.75% (A グレードの従来チップ) ±1.25% (標準グレードの従来チップ) ±0.5% (A グレードおよび標準グレードの新チップ) 負荷および温度に対する出力電圧 (VOUT) 精度：±1% (新チップ) 出力電流：最大 100mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：620μA (ILOAD = 100 mA の場合) シャットダウン電流と温度との関係： < 1μA (従来チップ) ≤ 1.75μA (新チップ) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作 (新チップ) 高 PSRR (新チップ)： 1kHz で 75dB、1MHz で 45dB 動作時接合部温度：-40℃～+125℃ パッケージ：5 ピン SOT-23 (DBV) 入力電圧 (VIN) 範囲： 従来のチップ：2.1 V ～ 16 V 新しいチップ：2.5V～16V IN 従来のチップ：2.1 V ～ 16 V 新しいチップ：2.5V～16V 従来のチップ：2.1 V ～ 16 V新しいチップ：2.5V～16V出力電圧 (VOUT) 範囲：1.2 V ～ 5.0 VOUT出力電圧 (VOUT) 精度： ±0.75% (A グレードの従来チップ) ±1.25% (標準グレードの従来チップ) ±0.5% (A グレードおよび標準グレードの新チップ) OUT ±0.75% (A グレードの従来チップ) ±1.25% (標準グレードの従来チップ) ±0.5% (A グレードおよび標準グレードの新チップ) ±0.75% (A グレードの従来チップ)±1.25% (標準グレードの従来チップ)±0.5% (A グレードおよび標準グレードの新チップ)負荷および温度に対する出力電圧 (VOUT) 精度：±1% (新チップ)OUT出力電流：最大 100mA低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合)QLOAD低い IQ (新チップ)：620μA (ILOAD = 100 mA の場合)QLOADシャットダウン電流と温度との関係： < 1μA (従来チップ) ≤ 1.75μA (新チップ) < 1μA (従来チップ) ≤ 1.75μA (新チップ) < 1μA (従来チップ)≤ 1.75μA (新チップ)出力電流制限および過熱保護2.2µF のセラミック・コンデンサで安定動作 (新チップ)高 PSRR (新チップ)： 1kHz で 75dB、1MHz で 45dB 1kHz で 75dB、1MHz で 45dB 1kHz で 75dB、1MHz で 45dB動作時接合部温度：-40℃～+125℃パッケージ：5 ピン SOT-23 (DBV) アプリケーション 電気メーター マイクロ インバータ サーバー PSU (12V 出力) 住宅用ブレーカ アプリケーション 電気メーター マイクロ インバータ サーバー PSU (12V 出力) 住宅用ブレーカ 電気メーター マイクロ インバータ サーバー PSU (12V 出力) 住宅用ブレーカ 電気メーター マイクロ インバータ サーバー PSU (12V 出力) 住宅用ブレーカ 電気メーター 電気メーター マイクロ インバータ マイクロ インバータ サーバー PSU (12V 出力) サーバー PSU (12V 出力) 住宅用ブレーカ 住宅用ブレーカ 概要 L 「Nine」を「Assorted」に変更 yes L 「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 yes N 代表的なアプリケーションの図を更新し、ピン名を Vin、Vout から IN、OUT に変更 yes LP2981-N は、固定出力、低ドロップアウト (LDO) の電圧レギュレータで、2.5V～16V の入力電圧範囲 (新チップの場合のみ) と最大 100mA の負荷電流に対応します。LP2981-N は、1.2V～5.0V の出力範囲をサポートしています (新チップ)。 さらに、LP2981-N (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。 新チップの広帯域の PSRR 特性は、1kHz で 75dB、1MHz で 45dB であり、上流の DC/DC コンバータのスイッチング周波数を減衰して、レギュレータ後のフィルタ処理を最小化できます。 内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 パッケージ情報 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA LP2981-N SOT-23 (5) 2.90mm × 2.80mm 利用可能なすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。 パッケージ・サイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。 代表的なアプリケーション回路 ドロップアウト電圧と温度との関係 (新チップ) 概要 L 「Nine」を「Assorted」に変更 yes L 「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 yes N 代表的なアプリケーションの図を更新し、ピン名を Vin、Vout から IN、OUT に変更 yes L 「Nine」を「Assorted」に変更 yes L 「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 yes N 代表的なアプリケーションの図を更新し、ピン名を Vin、Vout から IN、OUT に変更 yes L 「Nine」を「Assorted」に変更 yes L「Nine」を「Assorted」に変更yes L 「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 yes L「ピン構成および機能」セクション、「ESD 定格」表、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加 yes N 代表的なアプリケーションの図を更新し、ピン名を Vin、Vout から IN、OUT に変更 yes N代表的なアプリケーションの図を更新し、ピン名を Vin、Vout から IN、OUT に変更yes LP2981-N は、固定出力、低ドロップアウト (LDO) の電圧レギュレータで、2.5V～16V の入力電圧範囲 (新チップの場合のみ) と最大 100mA の負荷電流に対応します。LP2981-N は、1.2V～5.0V の出力範囲をサポートしています (新チップ)。 さらに、LP2981-N (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。 新チップの広帯域の PSRR 特性は、1kHz で 75dB、1MHz で 45dB であり、上流の DC/DC コンバータのスイッチング周波数を減衰して、レギュレータ後のフィルタ処理を最小化できます。 内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 パッケージ情報 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA LP2981-N SOT-23 (5) 2.90mm × 2.80mm 利用可能なすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。 パッケージ・サイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。 代表的なアプリケーション回路 ドロップアウト電圧と温度との関係 (新チップ) LP2981-N は、固定出力、低ドロップアウト (LDO) の電圧レギュレータで、2.5V～16V の入力電圧範囲 (新チップの場合のみ) と最大 100mA の負荷電流に対応します。LP2981-N は、1.2V～5.0V の出力範囲をサポートしています (新チップ)。 さらに、LP2981-N (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。 新チップの広帯域の PSRR 特性は、1kHz で 75dB、1MHz で 45dB であり、上流の DC/DC コンバータのスイッチング周波数を減衰して、レギュレータ後のフィルタ処理を最小化できます。 内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 パッケージ情報 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA LP2981-N SOT-23 (5) 2.90mm × 2.80mm 利用可能なすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。 パッケージ・サイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。 代表的なアプリケーション回路 ドロップアウト電圧と温度との関係 (新チップ) LP2981-N は、固定出力、低ドロップアウト (LDO) の電圧レギュレータで、2.5V～16V の入力電圧範囲 (新チップの場合のみ) と最大 100mA の負荷電流に対応します。LP2981-N は、1.2V～5.0V の出力範囲をサポートしています (新チップ)。さらに、LP2981-N (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。新チップの広帯域の PSRR 特性は、1kHz で 75dB、1MHz で 45dB であり、上流の DC/DC コンバータのスイッチング周波数を減衰して、レギュレータ後のフィルタ処理を最小化できます。内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 パッケージ情報 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA LP2981-N SOT-23 (5) 2.90mm × 2.80mm パッケージ情報 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA LP2981-N SOT-23 (5) 2.90mm × 2.80mm 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA 部品番号 パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE 本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA 部品番号パッケージ#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE #GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/DEVINFONOTE本体サイズ (公称)#GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA #GUID-EA205ADA-1978-4F90-B175-359780AD4E2D/GUID-24D7D1E5-22BE-40CF-962F-22610CD1EDFA LP2981-N SOT-23 (5) 2.90mm × 2.80mm LP2981-N SOT-23 (5) 2.90mm × 2.80mm LP2981-NSOT-23 (5)2.90mm × 2.80mm 利用可能なすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。 パッケージ・サイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。 利用可能なすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。パッケージ・サイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。 代表的なアプリケーション回路 ドロップアウト電圧と温度との関係 (新チップ) 代表的なアプリケーション回路 代表的なアプリケーション回路 ドロップアウト電圧と温度との関係 (新チップ) ドロップアウト電圧と温度との関係 (新チップ) Table of Contents yes Table of Contents yes yes yes Pin Configuration and Functions DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. Pin Configuration and Functions DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. DBV Package, 5-Pin SOT-23 (Top View) DBV Package, 5-Pin SOT-23 (Top View) DBV Package,5-Pin SOT-23(Top View) Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. PIN TYPE DESCRIPTION NO. NAME PIN TYPE DESCRIPTION PINTYPEDESCRIPTION NO. NAME NO.NAME 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. 1 IN I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 1INIInput supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See the section for more information. 2 GND — Common ground (device substrate). 2GND—Common ground (device substrate). 3 ON/OFF I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. 3ON/OFF OFFIEnable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused.OFF IN 4 NC — For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. 4NC—For new chip: Not internally connected. This pin can be left open or tied to ground for improved thermal performance.For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance. For legacy chip: DO NOT CONNECT. Device pin 4 is reserved for post packaging test and calibration of the LP2981-N VOUT accuracy. Device pin 4 must be left floating. Do not connect to any potential. Do not connect to ground. Any attempt to do pin continuity testing on device pin 4 is discouraged. Continuity test results will be variable depending on the actions of the factory calibration. Aggressive pin continuity testing (high voltage, or high current) on device pin 4 can activate the trim circuitry forcing VOUT to move out of tolerance.OUTOUT 5 OUT O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. 5OUTOOutput of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground. See the section for more information. Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.1 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. Thermal Information THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Electrical Characteristics specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 800 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA Legacy chip (Standard version) 150 New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Typical Characteristics Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF all voltage options, ON/ OFF pin tied to VIN. Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 5.0 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.0 V Output Voltage versus V_IN (New Chip) VOUT = 3.3 V Output Voltage versus V_IN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation versus V_IN & Temperature (New Chip) VOUT = 3.3 , IL = 1 mA Dropout Voltage (V_DO) versus Temperature (Legacy Chip) Dropout Voltage (V_DO) versus Temperature (New Chip) Dropout Voltage (V_DO) versus Load Current (Legacy Chip) Dropout Voltage (V_DO) versus Load Current (New Chip) Ground Pin Current (I_GND) versus Temperature (Legacy Chip) Ground Pin Current (I_GND) versus Temperature (New Chip) Ground Pin Current (I_GND) versus Load Current (Legacy Chip) Ground Pin Current (I_GND) versus Load Current (New Chip) Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = ∞ and RL = 5 kΩ Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = 500 Ω and RL = 50 Ω Input Current versus Input Voltage (V_IN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Time (New Chip) VIN = 6.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V Short Circuit Current versus Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Output Voltage (V_OUT) (New Chip) Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip) Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip) Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip) Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip) Input-to-Output Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (New Chip) Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip) ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 4.3 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 16.0 V ON/ OFF Threshold versus Temperature (Legacy Chip) ON/ OFF Threshold versus Temperature (New Chip) Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 MIN MAX UNIT MIN MAX UNIT MINMAXUNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 Input-output voltage (for new chip) –0.3 18 Current Maximum output current Internally limited mA Temperature Operating junction, TJ –55 150 °C Storage, Tstg –65 150 VIN Continuous input voltage range (for legacy chip) –0.3 16 V VIN IN Continuous input voltage range (for legacy chip)–0.316V Continuous input voltage range (for new chip) –0.3 18 Continuous input voltage range (for new chip) –0.318 VOUT Output voltage range (for legacy chip) –0.3 9 VOUT OUTOutput voltage range (for legacy chip)–0.39 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) Output voltage range (for new chip) –0.3VIN + 0.3 or 9 (whichever is smaller)IN VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 VON/OFF ON/OFF OFFON/OFF pin voltage range (for legacy chip)OFF–0.316 ON/OFF pin voltage range (for new chip) –0.3 18 ON/OFF pin voltage range (for new chip)OFF–0.318 VIN – VOUT Input-output voltage (for legacy chip) –0.3 16 VIN – VOUT INOUTInput-output voltage (for legacy chip)–0.316 Input-output voltage (for new chip) –0.3 18 Input-output voltage (for new chip)–0.318 Current Maximum output current Internally limited mA CurrentMaximum output currentInternally limitedmA Temperature Operating junction, TJ –55 150 °C TemperatureOperating junction, TJ J–55150°C Storage, Tstg –65 150 Storage, Tstg stg–65150 ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 VALUE (Legacy Chip) VALUE (New Chip) UNIT VALUE (Legacy Chip) VALUE (New Chip) UNIT VALUE (Legacy Chip)VALUE (New Chip)UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±2000 ±3000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1±2000±3000V Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 ±1000 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 N/A ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1N/A±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.1 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.1 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.1 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.1 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VIN Supply input voltage (for legacy chip) 2.1 16 V Supply input voltage (for new chip) 2.5 16 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 Input-output differential (for new chip) 0 16 VOUT Output voltage (for new chip) 1.2 5 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 100 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF COUT Output capacitor (for legacy chip)  2.2 4.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 TJ Operating junction temperature –40 125 °C VIN Supply input voltage (for legacy chip) 2.1 16 V VIN INSupply input voltage (for legacy chip)2.116V Supply input voltage (for new chip) 2.5 16 Supply input voltage (for new chip)2.516 VIN – VOUT Input-output differential (for legacy chip) 0.7 11 VIN – VOUT INOUTInput-output differential (for legacy chip)0.711 Input-output differential (for new chip) 0 16 Input-output differential (for new chip)016 VOUT Output voltage (for new chip) 1.2 5 VOUT OUTOutput voltage (for new chip)1.25 VON/OFF Enable voltage (for legacy chip) 0 VIN VON/OFF ON/OFF OFFEnable voltage (for legacy chip)0VIN IN Enable voltage (for new chip) 0 16 Enable voltage (for new chip)016 IOUT Output current 0 100 mA IOUT OUTOutput current0100mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 Input capacitor 1 µF CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 IN#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1Input capacitor1µF COUT Output capacitor (for legacy chip)  2.2 4.7 COUT OUTOutput capacitor (for legacy chip) 2.24.7 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 1 2.2 200 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF112.2200 TJ Operating junction temperature –40 125 °C TJ JOperating junction temperature–40125°C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability. Thermal Information THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Thermal Information THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 UNIT THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/APPNOTE_LP2985_SF1_SF1Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377648/THERMALFOOTER_SF1_SF1_SF1UNIT DBV (SOT23-5) DBV (SOT23-5) DBV (SOT23-5)DBV (SOT23-5) 5 PINS 5 PINS 5 PINS5 PINS RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W RθJA Junction-to-ambient thermal resistance 175.7 178.6 °C/W RθJA θJAJunction-to-ambient thermal resistance175.7178.6°C/W RθJC(top) Junction-to-case (top) thermal resistance 78.0 77.9 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance78.077.9°C/W RθJB Junction-to-board thermal resistance 30.8 47.2 °C/W RθJB θJBJunction-to-board thermal resistance30.847.2°C/W ψJT Junction-to-top characterization parameter 2.8 15.9 °C/W ψJT JTJunction-to-top characterization parameter2.815.9°C/W ψJB Junction-to-board characterization parameter 30.3 46.9 °C/W ψJB JBJunction-to-board characterization parameter30.346.9°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/AN/A°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal MetricsThermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Impact of board layout on LDO thermal performance Impact of board layout on LDO thermal performance Electrical Characteristics specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 800 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA Legacy chip (Standard version) 150 New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Electrical Characteristics specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 800 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA Legacy chip (Standard version) 150 New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 800 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA Legacy chip (Standard version) 150 New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)JINOUT(nom)OUTON/OFFINOUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 800 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA Legacy chip (Standard version) 150 New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % Legacy chip (A grade) –0.75 0.75 % New chip –0.5 0.5 % 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % Legacy chip (A grade) –1.0 1.0 % New chip –0.5 0.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % Legacy chip (A grade) –2.5 2.5 % New chip –1 1 % ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 New chip 3 IOUT = 1 mA Legacy chip 7 10 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 17 IOUT = 25 mA Legacy chip 70 100 New chip 110 132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 New chip 167 IOUT = 100 mA Legacy chip 200 250 New chip 160 175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 New chip 218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 80 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 25 mA Legacy chip 200 300 New chip 225 295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 New chip 345 IOUT = 100 mA Legacy chip 600 800 New chip 620 790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 New chip 950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA New chip 150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 New chip –0.9 VON/OFF = 5 V Legacy chip 5 New chip 0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 New chip 2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA Legacy chip (Standard version) 150 New chip 350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB New chip 75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd- Reset, temperature decreasing 150 ∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (Standard grade) –1.25 1.25 % ∆VOUT OUTOutput voltage toleranceIL = 1 mALLegacy chip (Standard grade)–1.251.25% Legacy chip (A grade) –0.75 0.75 % Legacy chip (A grade)–0.750.75% New chip –0.5 0.5 % New chip–0.50.5% 1 mA < IL < 100 mA Legacy chip (Standard grade) –2.0 2.0 % 1 mA < IL < 100 mALLegacy chip (Standard grade)–2.02.0% Legacy chip (A grade) –1.0 1.0 % Legacy chip (A grade)–1.01.0% New chip –0.5 0.5 % New chip–0.50.5% 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (Standard grade) –3.5 3.5 % 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°CLJ Legacy chip (Standard grade)–3.53.5% Legacy chip (A grade) –2.5 2.5 % Legacy chip (A grade)–2.52.5% New chip –1 1 % New chip–11% ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V ΔVOUT(ΔVIN) OUT(ΔVIN)Line regulationVO(NOM) + 1 V ≤ VIN ≤ 16 VO(NOM)INLegacy chip0.0070.014%/V New chip 0.002 0.014 New chip0.0020.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CO(NOM)INJLegacy chip0.0070.032 New chip 0.002 0.032 New chip0.0020.032 ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A ΔVOUT(ΔILOAD) OUT(ΔILOAD)Load regulation1 mA < IL < 100 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 VLJ INO(NOM)New chip0.10.5%/A VIN - VOUT Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 IOUT = 0 mA Legacy chip 1 3 mV VIN - VOUT INOUTDropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378394/A_ADB32FDA_4B69_4620_B527_3EA69A0F23FF_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1IOUT = 0 mAOUTLegacy chip13mV New chip 1 2.75 New chip12.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip5 New chip 3 New chip3 IOUT = 1 mA Legacy chip 7 10 IOUT = 1 mAOUTLegacy chip710 New chip 11.5 14 New chip11.514 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip15 New chip 17 New chip17 IOUT = 25 mA Legacy chip 70 100 IOUT = 25 mAOUTLegacy chip70100 New chip 110 132 New chip110132 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 150 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip150 New chip 167 New chip167 IOUT = 100 mA Legacy chip 200 250 IOUT = 100 mAOUTLegacy chip200250 New chip 160 175 New chip160175 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 375 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip375 New chip 218 New chip218 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA IGND GND GND pin currentIOUT = 0 mAOUTLegacy chip6595µA New chip 69 95 New chip6995 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip125 New chip 123 New chip123 IOUT = 1 mA Legacy chip 80 110 IOUT = 1 mAOUTLegacy chip80110 New chip 78 110 New chip78110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip170 New chip 140 New chip140 IOUT = 25 mA Legacy chip 200 300 IOUT = 25 mAOUTLegacy chip200300 New chip 225 295 New chip225295 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 550 IOUT = 25 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip550 New chip 345 New chip345 IOUT = 100 mA Legacy chip 600 800 IOUT = 100 mAOUTLegacy chip600800 New chip 620 790 New chip620790 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1500 IOUT = 100 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip1500 New chip 950 New chip950 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 VON/OFF < 0.3 V, VIN = 16 VON/OFFINLegacy chip0.010.8 New chip 1.25 1.75 New chip1.251.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°CON/OFFINJ Legacy chip0.052 New chip 1.12 2.75 New chip1.122.75 VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V VUVLO+ UVLO+Rising bias supply UVLOVIN rising, –40°C ≤ TJ ≤ 125°CINJ New chip2.22.4V VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 VUVLO- UVLO-Falling bias supply UVLOVIN falling, –40°C ≤ TJ ≤ 125°CINJ 1.9 VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 VUVLO(HYST) UVLO(HYST)UVLO hysteresis–40°C ≤ TJ ≤ 125°CJ 0.130 IO(SC) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA IO(SC) O(SC)Short Output CurrentRL = 0 Ω (steady state)LLegacy chip150mA New chip 150 New chip150 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.5 V VON/OFF ON/OFF OFFON/OFF input voltageOFFLow = Output OFFLegacy chip0.5V New chip 0.72 New chip0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°COUTINJ Legacy chip0.15 New chip 0.15 New chip0.15 High = Output ON Legacy chip 1.4 High = Output ONLegacy chip1.4 New chip 0.85 New chip0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°COUTINJ Legacy chip1.6 New chip 1.6 New chip1.6 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA ION/OFF ON/OFF OFFON/OFF input currentVON/OFF = 0 VON/OFFLegacy chip0.01µA New chip 0.42 New chip0.42 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –1 VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CON/OFFOUTINJ Legacy chip–1 New chip –0.9 New chip–0.9 VON/OFF = 5 V Legacy chip 5 VON/OFF = 5 VON/OFFLegacy chip5 New chip 0.011 New chip0.011 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 VON/OFF = 5 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CON/OFFOUTINJ Legacy chip15 New chip 2.20 New chip2.20 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip (A version) 150 400 mA IO(PK)Peak output currentVOUT ≥ VO(NOM) –5% (steady state)OUTO(NOM)Legacy chip (A version)150400mA Legacy chip (Standard version) 150 Legacy chip (Standard version)150 New chip 350 New chip350 ΔVO/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF Legacy chip 63 dB ΔVO/ΔVIN OINRipple Rejectionf = 1 kHz, COUT = 10 µFOUTLegacy chip63dB New chip 75 New chip75 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA Legacy chip 160 µVRMS Vn nOutput noise voltageBandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mAOUT OUTLOADLegacy chip160µVRMS VRMS Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA New chip 140 Bandwidth = 300 Hz to 50 kHz, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mAOUT OUTLOADNew chip140 Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C Tsd+ sd+Thermal shutdown thresholdShutdown, temperature increasingNew chip170°C Tsd- Reset, temperature decreasing 150 Tsd- sd-Reset, temperature decreasing150 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1-V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.DODOINOUT(nom) Typical Characteristics Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF all voltage options, ON/ OFF pin tied to VIN. Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 5.0 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.0 V Output Voltage versus V_IN (New Chip) VOUT = 3.3 V Output Voltage versus V_IN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation versus V_IN & Temperature (New Chip) VOUT = 3.3 , IL = 1 mA Dropout Voltage (V_DO) versus Temperature (Legacy Chip) Dropout Voltage (V_DO) versus Temperature (New Chip) Dropout Voltage (V_DO) versus Load Current (Legacy Chip) Dropout Voltage (V_DO) versus Load Current (New Chip) Ground Pin Current (I_GND) versus Temperature (Legacy Chip) Ground Pin Current (I_GND) versus Temperature (New Chip) Ground Pin Current (I_GND) versus Load Current (Legacy Chip) Ground Pin Current (I_GND) versus Load Current (New Chip) Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = ∞ and RL = 5 kΩ Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = 500 Ω and RL = 50 Ω Input Current versus Input Voltage (V_IN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Time (New Chip) VIN = 6.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V Short Circuit Current versus Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Output Voltage (V_OUT) (New Chip) Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip) Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip) Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip) Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip) Input-to-Output Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (New Chip) Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip) ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 4.3 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 16.0 V ON/ OFF Threshold versus Temperature (Legacy Chip) ON/ OFF Threshold versus Temperature (New Chip) Typical Characteristics Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF all voltage options, ON/ OFF pin tied to VIN. Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 5.0 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.0 V Output Voltage versus V_IN (New Chip) VOUT = 3.3 V Output Voltage versus V_IN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation versus V_IN & Temperature (New Chip) VOUT = 3.3 , IL = 1 mA Dropout Voltage (V_DO) versus Temperature (Legacy Chip) Dropout Voltage (V_DO) versus Temperature (New Chip) Dropout Voltage (V_DO) versus Load Current (Legacy Chip) Dropout Voltage (V_DO) versus Load Current (New Chip) Ground Pin Current (I_GND) versus Temperature (Legacy Chip) Ground Pin Current (I_GND) versus Temperature (New Chip) Ground Pin Current (I_GND) versus Load Current (Legacy Chip) Ground Pin Current (I_GND) versus Load Current (New Chip) Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = ∞ and RL = 5 kΩ Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = 500 Ω and RL = 50 Ω Input Current versus Input Voltage (V_IN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Time (New Chip) VIN = 6.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V Short Circuit Current versus Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Output Voltage (V_OUT) (New Chip) Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip) Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip) Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip) Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip) Input-to-Output Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (New Chip) Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip) ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 4.3 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 16.0 V ON/ OFF Threshold versus Temperature (Legacy Chip) ON/ OFF Threshold versus Temperature (New Chip) Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF all voltage options, ON/ OFF pin tied to VIN. Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 5.0 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.0 V Output Voltage versus V_IN (New Chip) VOUT = 3.3 V Output Voltage versus V_IN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation versus V_IN & Temperature (New Chip) VOUT = 3.3 , IL = 1 mA Dropout Voltage (V_DO) versus Temperature (Legacy Chip) Dropout Voltage (V_DO) versus Temperature (New Chip) Dropout Voltage (V_DO) versus Load Current (Legacy Chip) Dropout Voltage (V_DO) versus Load Current (New Chip) Ground Pin Current (I_GND) versus Temperature (Legacy Chip) Ground Pin Current (I_GND) versus Temperature (New Chip) Ground Pin Current (I_GND) versus Load Current (Legacy Chip) Ground Pin Current (I_GND) versus Load Current (New Chip) Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = ∞ and RL = 5 kΩ Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = 500 Ω and RL = 50 Ω Input Current versus Input Voltage (V_IN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Time (New Chip) VIN = 6.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V Short Circuit Current versus Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Output Voltage (V_OUT) (New Chip) Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip) Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip) Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip) Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip) Input-to-Output Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (New Chip) Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip) ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 4.3 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 16.0 V ON/ OFF Threshold versus Temperature (Legacy Chip) ON/ OFF Threshold versus Temperature (New Chip) Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF all voltage options, ON/ OFF pin tied to VIN.AINO(NOM)OUTINOFFIN Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 5.0 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip) VOUT = 3.0 V Output Voltage versus V_IN (New Chip) VOUT = 3.3 V Output Voltage versus V_IN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Line Regulation versus V_IN & Temperature (New Chip) VOUT = 3.3 , IL = 1 mA Dropout Voltage (V_DO) versus Temperature (Legacy Chip) Dropout Voltage (V_DO) versus Temperature (New Chip) Dropout Voltage (V_DO) versus Load Current (Legacy Chip) Dropout Voltage (V_DO) versus Load Current (New Chip) Ground Pin Current (I_GND) versus Temperature (Legacy Chip) Ground Pin Current (I_GND) versus Temperature (New Chip) Ground Pin Current (I_GND) versus Load Current (Legacy Chip) Ground Pin Current (I_GND) versus Load Current (New Chip) Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = ∞ and RL = 5 kΩ Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = 500 Ω and RL = 50 Ω Input Current versus Input Voltage (V_IN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Time (New Chip) VIN = 6.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V Short Circuit Current versus Time (New Chip) VIN = 16.0 V Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Output Voltage (V_OUT) (New Chip) Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip) Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip) Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip) Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip) Input-to-Output Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (New Chip) Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip) ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 4.3 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 16.0 V ON/ OFF Threshold versus Temperature (Legacy Chip) ON/ OFF Threshold versus Temperature (New Chip) Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V Output Voltage versus Temperature (Legacy Chip) VIN = 6 V, VOUT = 5 V VIN = 6 V, VOUT = 5 V VIN = 6 V, VOUT = 5 V VIN = 6 V, VOUT = 5 V VIN = 6 V, VOUT = 5 V VIN = 6 V, VOUT = 5 VINOUT Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 VINOUT Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V Output Voltage versus Temperature (Legacy Chip) VIN = 4.0 V, VOUT = 3.0 V VIN = 4.0 V, VOUT = 3.0 V VIN = 4.0 V, VOUT = 3.0 V VIN = 4.0 V, VOUT = 3.0 V VIN = 4.0 V, VOUT = 3.0 V VIN = 4.0 V, VOUT = 3.0 VINOUT Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V Output Voltage versus Temperature (New Chip) VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 V VIN = 4.3 V, VOUT = 3.3 VINOUT Output Voltage versus V_IN (Legacy Chip) VOUT = 5.0 V Output Voltage versus V_IN (Legacy Chip)IN VOUT = 5.0 V VOUT = 5.0 V VOUT = 5.0 V VOUT = 5.0 V VOUT = 5.0 V VOUT = 5.0 VOUT Output Voltage versus V_IN (Legacy Chip) VOUT = 3.3 V Output Voltage versus V_IN (Legacy Chip)IN VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 VOUT Output Voltage versus V_IN (Legacy Chip) VOUT = 3.0 V Output Voltage versus V_IN (Legacy Chip)IN VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 VOUT Output Voltage versus V_IN (New Chip) VOUT = 3.3 V Output Voltage versus V_IN (New Chip)IN VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 V VOUT = 3.3 VOUT Output Voltage versus V_IN and Temperature (New Chip) VOUT = 3.3 V, IL = 1 mA Output Voltage versus V_IN and Temperature (New Chip)IN VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Line Regulation versus V_IN & Temperature (New Chip) VOUT = 3.3 , IL = 1 mA Line Regulation versus V_IN & Temperature (New Chip)IN VOUT = 3.3 , IL = 1 mA VOUT = 3.3 , IL = 1 mA VOUT = 3.3 , IL = 1 mA VOUT = 3.3 , IL = 1 mA VOUT = 3.3 , IL = 1 mA VOUT = 3.3 , IL = 1 mAOUTL Dropout Voltage (V_DO) versus Temperature (Legacy Chip) Dropout Voltage (V_DO) versus Temperature (Legacy Chip)DO Dropout Voltage (V_DO) versus Temperature (New Chip) Dropout Voltage (V_DO) versus Temperature (New Chip)DO Dropout Voltage (V_DO) versus Load Current (Legacy Chip) Dropout Voltage (V_DO) versus Load Current (Legacy Chip)DO Dropout Voltage (V_DO) versus Load Current (New Chip) Dropout Voltage (V_DO) versus Load Current (New Chip)DO Ground Pin Current (I_GND) versus Temperature (Legacy Chip) Ground Pin Current (I_GND) versus Temperature (Legacy Chip)GND Ground Pin Current (I_GND) versus Temperature (New Chip) Ground Pin Current (I_GND) versus Temperature (New Chip)GND Ground Pin Current (I_GND) versus Load Current (Legacy Chip) Ground Pin Current (I_GND) versus Load Current (Legacy Chip)GND Ground Pin Current (I_GND) versus Load Current (New Chip) Ground Pin Current (I_GND) versus Load Current (New Chip)GND Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = ∞ and RL = 5 kΩ Input Current versus Input Voltage (V_IN) (Legacy Chip)IN VOUT = 5 V, RL = ∞ and RL = 5 kΩ VOUT = 5 V, RL = ∞ and RL = 5 kΩ VOUT = 5 V, RL = ∞ and RL = 5 kΩ VOUT = 5 V, RL = ∞ and RL = 5 kΩ VOUT = 5 V, RL = ∞ and RL = 5 kΩ VOUT = 5 V, RL = ∞ and RL = 5 kΩOUTLL Input Current versus Input Voltage (V_IN) (Legacy Chip) VOUT = 5 V, RL = 500 Ω and RL = 50 Ω Input Current versus Input Voltage (V_IN) (Legacy Chip)IN VOUT = 5 V, RL = 500 Ω and RL = 50 Ω VOUT = 5 V, RL = 500 Ω and RL = 50 Ω VOUT = 5 V, RL = 500 Ω and RL = 50 Ω VOUT = 5 V, RL = 500 Ω and RL = 50 Ω VOUT = 5 V, RL = 500 Ω and RL = 50 Ω VOUT = 5 V, RL = 500 Ω and RL = 50 ΩOUTLL Input Current versus Input Voltage (V_IN) (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Input Current versus Input Voltage (V_IN) (New Chip)IN VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩOUTL Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mAOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mAOUTL Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mAOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μFOUTOUT Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μFOUTOUT Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μFOUTOUT Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μFOUTOUT Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μFOUTOUT Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 VIN Short Circuit Current versus Time (New Chip) VIN = 6.0 V Short Circuit Current versus Time (New Chip) VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 VIN Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V Short Circuit Current versus Time (Legacy Chip) VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 VIN Short Circuit Current versus Time (New Chip) VIN = 16.0 V Short Circuit Current versus Time (New Chip) VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 VIN Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (Legacy Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Instantaneous Short Circuit Current versus Temperature (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip) VIN = 6.0 V Short Circuit Current versus Output Voltage (V_OUT) (Legacy Chip)OUT VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 V VIN = 6.0 VIN Short Circuit Current versus Output Voltage (V_OUT) (New Chip) Short Circuit Current versus Output Voltage (V_OUT) (New Chip)OUT Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V OUT Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V Output Impedance versus Frequency (Legacy Chip) VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V VOUT = 3.0 V OUT Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Frequency (Legacy Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip) Ripple Rejection versus Load Current (I_L) & Frequency (New Chip)L Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip) Ripple Rejection versus Output Capacitor (C_L) & Frequency (New Chip)L Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Frequency (Legacy Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip) Output Noise Density versus Load Current (I_L) Frequency (New Chip)L Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip) Output Noise Density versus Output Capacitor (C_L) Frequency (New Chip)L Input-to-Output Leakage versus Temperature (Legacy Chip) Input-to-Output Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (Legacy Chip) Output Reverse Leakage versus Temperature (New Chip) Output Reverse Leakage versus Temperature (New Chip) Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩOUTL Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip) ON/ OFF Pin Current versus V_{ON/ OFF} (Legacy Chip)OFFON/ OFF OFF ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 4.3 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip)OFFON/ OFF OFF VIN = 4.3 V VIN = 4.3 V VIN = 4.3 V VIN = 4.3 V VIN = 4.3 V VIN = 4.3 VIN ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip) VIN = 16.0 V ON/ OFF Pin Current versus V_{ON/ OFF} (New Chip)OFFON/ OFF OFF VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 V VIN = 16.0 VIN ON/ OFF Threshold versus Temperature (Legacy Chip) ON/ OFF Threshold versus Temperature (Legacy Chip)OFF ON/ OFF Threshold versus Temperature (New Chip) ON/ OFF Threshold versus Temperature (New Chip)OFF Detailed Description Overview The LP2981-N is a fixed-output, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C. Functional Block Diagram Feature Description Output Enable F Added Output Enable section no The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. Dropout Voltage F Added Dropout Voltage section no Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Current Limit F Added Current Limit section no The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Thermal Shutdown F Added Thermal Shutdown section no The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Limits for Thermal shutdown circuit are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Output Pulldown F Added Output Pulldown section no The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Device Functional Modes Device Functional Mode Comparison #GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Detailed Description Overview The LP2981-N is a fixed-output, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C. Overview The LP2981-N is a fixed-output, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C. The LP2981-N is a fixed-output, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C. The LP2981-N is a fixed-output, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and non-portable applications. The LP2981-N has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 100 mA of continuous load current.This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to +125°C. Functional Block Diagram Functional Block Diagram Feature Description Output Enable F Added Output Enable section no The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. Dropout Voltage F Added Dropout Voltage section no Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Current Limit F Added Current Limit section no The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Thermal Shutdown F Added Thermal Shutdown section no The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Limits for Thermal shutdown circuit are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Output Pulldown F Added Output Pulldown section no The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Feature Description Output Enable F Added Output Enable section no The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. Output Enable F Added Output Enable section no F Added Output Enable section no F Added Output Enable section no FAdded Output Enable sectionOutput Enableno The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. For the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage. The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled when the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device.OFFOFFOFFOFFOFFOFFFor the new chip, the device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin to actively discharge the output voltage.OFFOFF Dropout Voltage F Added Dropout Voltage section no Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Dropout Voltage F Added Dropout Voltage section no F Added Dropout Voltage section no F Added Dropout Voltage section no FAdded Dropout Voltage sectionDropout Voltageno Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. R D S ( O N ) =   V D O I R A T E D Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well.DOINOUTRATEDRATEDOUT For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. DS(ON)DS(ON) R D S ( O N ) =   V D O I R A T E D R D S ( O N ) =   V D O I R A T E D R D S ( O N ) =   V D O I R A T E D R D S ( O N ) R R D S ( O N ) DS(ON)=  V D O I R A T E D V D O V D O V V D O DO I R A T E D I R A T E D I I R A T E D RATED Current Limit F Added Current Limit section no The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Current Limit F Added Current Limit section no F Added Current Limit section no F Added Current Limit section no FAdded Current Limit sectionCurrent Limitno The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the Electrical Characteristics table.CLCLElectrical CharacteristicsThe output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note.INOUTCL Know Your Limits application noteKnow Your Limits shows a diagram of the current limit. Current Limit Current Limit Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Undervoltage Lockout (UVLO) F Added Undervoltage Lockout (UVLO) section no F Added Undervoltage Lockout (UVLO) section no F Added Undervoltage Lockout (UVLO) section no FAdded Undervoltage Lockout (UVLO) sectionUndervoltage Lockout (UVLO)no For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. For the new chip, the device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Thermal Shutdown F Added Thermal Shutdown section no The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Limits for Thermal shutdown circuit are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Thermal Shutdown F Added Thermal Shutdown section no F Added Thermal Shutdown section no F Added Thermal Shutdown section no FAdded Thermal Shutdown sectionThermal Shutdownno The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Limits for Thermal shutdown circuit are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Limits for Thermal shutdown circuit are defined in . The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis makes sure that the device resets (turns on) when the temperature falls to TSD(reset) (typical). Limits for Thermal shutdown circuit are defined in .JSD(shutdown)SD(reset) The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start-up completes.INOUTFor reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Output Pulldown F Added Output Pulldown section no The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Output Pulldown F Added Output Pulldown section no F Added Output Pulldown section no F Added Output Pulldown section no FAdded Output Pulldown sectionOutput Pulldownno The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO When the device is disabled (VON/OFF < VON/OFF(LOW))ON/OFF OFFON/OFF(LOW)OFFIf 1.0 V < VIN < VUVLO INUVLODo not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Device Functional Modes Device Functional Mode Comparison #GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Device Functional Modes Device Functional Mode Comparison #GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Device Functional Mode Comparison #GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) #GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) #GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 shows the conditions that lead to the different modes of operation. See the table for parameter values.#GUID-9F40E2BD-B2B7-4C55-A7E6-602BC8C321F5/X3048 Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ OPERATING MODE PARAMETER OPERATING MODEPARAMETER VIN VON/OFF IOUT TJ VIN INVON/OFF ON/OFF OFFIOUT OUTTJ J Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Normal operationVIN > VOUT(nom) + VDO and VIN > VIN(min) INOUT(nom)DOININ(min)VON/OFF > VON/OFF(HI) ON/OFF OFFON/OFF(HI)OFFIOUT < IOUT(max) OUTOUT(max)TJ < TSD(shutdown) JSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operationVIN(min) < VIN < VOUT(nom) + VDO IN(min)INOUT(nom)DOVON/OFF > VON/OFF(HI) ON/OFF OFFON/OFF(HI)OFFIOUT < IOUT(max) OUTOUT(max)TJ < TSD(shutdown) JSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device)VIN < VUVLO INUVLOVON/OFF < VON/OFF(LOW) ON/OFF OFFON/OFF(LOW)OFFNot applicableTJ > TSD(shutdown) JSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)OUT(nom)DOThe output current is less than the current limit (IOUT < ICL)OUTCLThe device junction temperature is less than the thermal shutdown temperature (TJ < TSD)JSDThe ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling thresholdOFFOFF Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations.When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region.INOUT(NOM)DOnotOUT(NOM)DO Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.OFFOFF Application and Implementation 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 Application Information The LP2981-N is a linear voltage regulator operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified for a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. Recommended Capacitor Types Recommended Capacitors for the Legacy Chip Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor. Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no Input capacitor: For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output capacitor: For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Estimating Junction Temperature F Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Power Dissipation (P_D) F Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Reverse Current F Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Typical Application LP2981-N Typical Application *ON/ OFF input must be actively terminated. Tie to VIN if this function is not to be used. Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin (see ). Design Requirements PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin. For the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs. Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Application and Implementation 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 Application Information The LP2981-N is a linear voltage regulator operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified for a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. Recommended Capacitor Types Recommended Capacitors for the Legacy Chip Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor. Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no Input capacitor: For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output capacitor: For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Estimating Junction Temperature F Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Power Dissipation (P_D) F Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Reverse Current F Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Application Information The LP2981-N is a linear voltage regulator operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified for a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. The LP2981-N is a linear voltage regulator operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified for a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. The LP2981-N is a linear voltage regulator operating from 2.5 V to 16 V (for new chip) on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across line, load and temperature) and 100-mA maximum output current.Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified for a solid design. If timing, start-up, noise, power supply rejection ratio (PSRR), or any other transient specification is required, then the design becomes more challenging. Recommended Capacitor Types Recommended Capacitors for the Legacy Chip Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor. Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. Recommended Capacitor Types Recommended Capacitors for the Legacy Chip Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor. Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Recommended Capacitors for the Legacy Chip Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor. Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high. Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor. Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze. Tantalum Capacitors: For the legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as ESR increases, a capacitor with ESR, near the upper limit for stability at room temperature can cause instability. For very low temperature applications, output tantalum capacitors can be used in parallel configuration to prevent the ESR from going up too high.Tantalum Capacitors: Ceramic Capacitors: For the legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output of the LDO. This is because the ESR of a ceramic can be low enough to go below the minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic capacitor is used on the output, a 1-Ω resistor is required be placed in series with the capacitor.Ceramic Capacitors: Aluminum Capacitors: For the legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO, because of the large physical size. These aluminimum capacitors must meet the same ESR requirements over the operating temperature range, more difficult because of their steep increase at cold temperature. An aluminum electrolytic can exhibit an ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum electrolytics are not operational below −25°C because the electrolyte can freeze.Aluminum Capacitors: Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. Recommended Capacitors for the New Chip The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. The new chip is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas using Y5V-rated capacitors is discouraged because of large variations in capacitance.Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in the table account for an effective capacitance of approximately 50% of the nominal value. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no Input capacitor: For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output capacitor: For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Input and Output Capacitor Requirements F Added Input and Output Capacitor Requirements section no F Added Input and Output Capacitor Requirements section no F Added Input and Output Capacitor Requirements section no FAdded Input and Output Capacitor Requirements sectionInput and Output Capacitor Requirementsno Input capacitor: For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output capacitor: For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Input capacitor: For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. For the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output capacitor: For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ). For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Input capacitor: Input capacitor:For the legacy chip, an input capacitor (CIN) ≥1 μF is required (the amount of capacitance can be increased without limit). Any good-quality tantalum or ceramic capacitor can be used. The capacitor must be located no more than half an inch from the input pin and returned to a clean analog ground. INFor the new chip, although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Output capacitor: Output capacitor:For the legacy chip, The output capacitor must meet both the requirement for minimum amount of capacitance and equivalent series resistance (ESR) value. Curves are provided which show the allowable ESR range as a function of load current for various output voltages and capacitor values (refer to , , , and ).For the new chip, Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor, preferably ceramic capacitors, within the range specified in the table for stability. Estimating Junction Temperature F Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Estimating Junction Temperature F Added Estimating Junction Temperature section no F Added Estimating Junction Temperature section no F Added Estimating Junction Temperature section no FAdded Estimating Junction Temperature sectionEstimating Junction Temperatureno The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. The Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature.Thermal InformationJTJBJJTTJBBTJ = TT + ψJT × PD JTJTDwhere: PD is the dissipated power TT is the temperature at the center-top of the device package PD is the dissipated powerDTT is the temperature at the center-top of the device packageTTJ = TB + ψJB × PD JBJBDwhere: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edgeBFor detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Semiconductor and IC Package Thermal Metrics application noteSemiconductor and IC Package Thermal Metrics Power Dissipation (P_D) F Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Power Dissipation (P_D)D F Added Power Dissipation (PD) section no F Added Power Dissipation (PD) section no F Added Power Dissipation (PD) section no FAdded Power Dissipation (PD) sectionPower Dissipation (PD)Dno Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization. Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress.To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD).DPD = (VIN – VOUT) × IOUT DINOUTOUTPower dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation.For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation.The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA).AθJAA TJ = TA + (RθJA × PD) JAθJADThermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. As mentioned in the An empirical analysis of the impact of board layout on LDO thermal performance application note, RθJA can be improved by 35% to 55% compared to the Thermal Information table value with the PCB board layout optimization.θJAThermal Information An empirical analysis of the impact of board layout on LDO thermal performance application noteAn empirical analysis of the impact of board layout on LDO thermal performanceθJAThermal Information Reverse Current F Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Reverse Current F Added Reverse Current section no F Added Reverse Current section no F Added Reverse Current section no FAdded Reverse Current sectionReverse Currentno Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device.Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V.OUTIN If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If the device has a large COUT and the input supply collapses with little or no load currentOUTThe output is biased when the input supply is not establishedThe output is biased above the input supplyIf reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Example Circuit for Reverse Current Protection Using a Schottky Diode Typical Application LP2981-N Typical Application *ON/ OFF input must be actively terminated. Tie to VIN if this function is not to be used. Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin (see ). Design Requirements PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin. For the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs. Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Typical Application LP2981-N Typical Application *ON/ OFF input must be actively terminated. Tie to VIN if this function is not to be used. Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin (see ). LP2981-N Typical Application *ON/ OFF input must be actively terminated. Tie to VIN if this function is not to be used. Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin (see ). LP2981-N Typical Application *ON/ OFF input must be actively terminated. Tie to VIN if this function is not to be used. Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin (see ). LP2981-N Typical Application*ON/ OFF input must be actively terminated. Tie to VIN if this function is not to be used. Minimum output capacitance is shown to insure stability over full load current range. More capacitance provides superior dynamic performance and additional stability margin (see ).OFFIN Design Requirements PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Design Requirements PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB PARAMETER DESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB PARAMETER DESIGN REQUIREMENT PARAMETER DESIGN REQUIREMENT PARAMETERDESIGN REQUIREMENT Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS PSRR at 1 kHz > 40 dB Input voltage 12 V ±10%, provided by the DC-DC converter switching at 1 MHz Input voltage12 V ±10%, provided by the DC-DC converter switching at 1 MHz Output voltage 3.3 V ±1% Output voltage3.3 V ±1% Output current 100 mA (maximum), 1 mA (minimum) Output current100 mA (maximum), 1 mA (minimum) RMS noise, 300 Hz to 50 kHz < 1 mVRMS RMS noise, 300 Hz to 50 kHz< 1 mVRMS RMS PSRR at 1 kHz > 40 dB PSRR at 1 kHz> 40 dB Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin. For the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs. Detailed Design Procedure ON and OFF Input Operation K Changed layout of National Data Sheet to TI format yes The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin. For the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs. ON and OFF Input OperationOFF K Changed layout of National Data Sheet to TI format yes K Changed layout of National Data Sheet to TI format yes K Changed layout of National Data Sheet to TI format yes KChanged layout of National Data Sheet to TI formatyes The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin. For the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs. The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating). For proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ). The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin. For the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs. The LP2981-N is shut off by pulling the ON/ OFF input low, and turned on by driving the input high. If this feature is not to be used, the ON/OFF input is required to be tied to VIN to keep the regulator on at all times (the ON/ OFF input must not be left floating).OFFINOFFnotFor proper operation of the LDO, the signal source used to drive the ON/ OFF input must be able to swing above and below the specified turnon/turnoff voltage thresholds which specify an ON or OFF state (see ).OFFOFF The ON/ OFF signal can come from either a totem-pole output, or an open-collector output with pullup resistor to the LP2981-N input voltage or another logic supply. The high-level voltage can exceed the LP2981-N input voltage, but must remain within the for the ON/ OFF pin.OFF OFFFor the legacy chip only, it is also important that the turnon/turnoff voltage signals applied to the ON/ OFF input have a slew rate which is greater than 40 mV/μs.OFF Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Application Curves 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF 5-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μF VOUT = 5 V, COUT = 3.3 μFOUTOUT 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF 5-V, 10-μF ESR Curves (Legacy Chip) VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μF VOUT = 5 V, CL = 10 μFOUTL 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF 3.0-V, 3.3-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μFOUTOUT 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF 3.0-V, 10-μF ESR Curves (Legacy Chip) VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μF VOUT = 3.0 V, CL = 10 μFOUTL Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mA VOUT = 5 V, IL = 100 mAOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mA VOUT = 3.3 V, IL = 100 mAOUTL Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA Line Transient Response (Legacy Chip) VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mA VOUT = 5 V, IL = 1 mAOUTL Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA Line Transient Response (New Chip) VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mA VOUT = 3.3 V, IL = 1 mAOUTL Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μF VOUT = 3.0 V, COUT = 3.3 μFOUTOUT Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μF VOUT = 3.0 V, COUT = 10 μFOUTOUT Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μF VOUT = 5.0 V, COUT = 3.3 μFOUTOUT Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF Load Transient Response (Legacy Chip) VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μF VOUT = 5.0 V, COUT = 10 μFOUTOUT Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF Load Transient Response (New Chip) VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μF VOUT = 3.3 V, COUT = 2.2 μFOUTOUT Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-on Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ Turn-on Waveform (New Chip) VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩ VOUT = 3.3 V, RL = 3.3 kΩOUTL Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (Legacy Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ Turn-off Waveform (New Chip) VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩ VOUT = 5 V, RL = 5 kΩOUTL Power Supply Recommendations The LP2981-N is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. Power Supply Recommendations The LP2981-N is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. The LP2981-N is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. The LP2981-N is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. The LP2981-N is designed to operate from an input voltage supply range between 2.5 V and 16 V (for the new chip). The input voltage range provides adequate headroom for the device to have a regulated output. This input supply must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance. Layout Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves for the accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. Layout Example LP2981-N Layout Example Layout Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves for the accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. Layout Guidelines For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves for the accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves for the accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. For best overall performance, place all circuit components on the same side of the circuit board and as near as practical to the respective LDO pin connections. Place ground return connections to the input and output capacitors, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves for the accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device. In most applications, this ground plane is necessary to meet thermal requirements. Layout Example LP2981-N Layout Example Layout Example LP2981-N Layout Example LP2981-N Layout Example LP2981-N Layout Example LP2981-N Layout Example Device and Documentation Support Device Nomenclature O Added Device Nomenclature section yes Available Options PRODUCT VOUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. サード・パーティ製品に関する免責事項 サード・パーティ製品またはサービスに関するテキサス・インスツルメンツの出版物は、単独またはテキサス・インスツルメンツの製品、サービスと一緒に提供される場合に関係なく、サード・パーティ製品またはサービスの適合性に関する是認、サード・パーティ製品またはサービスの是認の表明を意味するものではありません。 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Related Documentation H Added three references to Related Documentation yes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note サポート・リソース テキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。 Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 Device and Documentation Support Device Nomenclature O Added Device Nomenclature section yes Available Options PRODUCT VOUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. Device Nomenclature O Added Device Nomenclature section yes O Added Device Nomenclature section yes O Added Device Nomenclature section yes OAdded Device Nomenclature sectionDevice Nomenclatureyes Available Options PRODUCT VOUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. Available Options PRODUCT VOUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. Available Options PRODUCT VOUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. Available Options PRODUCT VOUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. PRODUCT VOUT PRODUCT VOUT PRODUCTVOUT OUT LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. LP2981cxxxzX-y.y/NOPBLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). LP2981cxxxzX-y.y/NOPBLegacy chip cxxxzXy.yLegacy chip c is the accuracy specification. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel. y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).cxxxzXy.y LP2981AxxxzX-y.y/M3 New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. LP2981AxxxzX-y.y/M3 New chip LP2981AxxxzX-y.y/M3 AxxxzXy.yM3New chip A is for higher accuracy and non-A is for standard grade. xxx is the package designator. z is the package quantity. X is for a large-quantity reel and non-X is for a small-quantity reel y.y is the nominal output voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V). M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology.AxxxzXy.yM3 サード・パーティ製品に関する免責事項 サード・パーティ製品またはサービスに関するテキサス・インスツルメンツの出版物は、単独またはテキサス・インスツルメンツの製品、サービスと一緒に提供される場合に関係なく、サード・パーティ製品またはサービスの適合性に関する是認、サード・パーティ製品またはサービスの是認の表明を意味するものではありません。 サード・パーティ製品に関する免責事項 サード・パーティ製品またはサービスに関するテキサス・インスツルメンツの出版物は、単独またはテキサス・インスツルメンツの製品、サービスと一緒に提供される場合に関係なく、サード・パーティ製品またはサービスの適合性に関する是認、サード・パーティ製品またはサービスの是認の表明を意味するものではありません。 サード・パーティ製品またはサービスに関するテキサス・インスツルメンツの出版物は、単独またはテキサス・インスツルメンツの製品、サービスと一緒に提供される場合に関係なく、サード・パーティ製品またはサービスの適合性に関する是認、サード・パーティ製品またはサービスの是認の表明を意味するものではありません。 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.Alert me Related Documentation H Added three references to Related Documentation yes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Related Documentation H Added three references to Related Documentation yes H Added three references to Related Documentation yes H Added three references to Related Documentation yes HAdded three references to Related Documentation Related Documentationyes For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note For related documentation see the following: Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Texas Instruments, LDO Noise Demystified , application note Texas Instruments, LDO PSRR Measurement Simplified , application note Texas Instruments, A Topical Index of TI LDO Application Notes , application note Texas Instruments, LDO Noise Demystified , application note LDO Noise Demystified LDO Noise DemystifiedTexas Instruments, LDO PSRR Measurement Simplified , application note LDO PSRR Measurement Simplified LDO PSRR Measurement SimplifiedTexas Instruments, A Topical Index of TI LDO Application Notes , application note A Topical Index of TI LDO Application Notes A Topical Index of TI LDO Application Notes サポート・リソース テキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。 サポート・リソース テキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。 テキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。 テキサス・インスツルメンツ E2E サポート・フォーラムテキサス・インスツルメンツ E2Eリンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。使用条件 Trademarks Trademarks 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 静電気放電に関する注意事項 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 用語集 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 この用語集には、用語や略語の一覧および定義が記載されています。 テキサス・インスツルメンツ用語集 テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。 Revision History yes April 2016 December 2023 N O Revision History yes April 2016 December 2023 N O yes April 2016 December 2023 N O yesApril 2016December 2023NO Revision History yes September 2015 April 2016 M N Revision History yes September 2015 April 2016 M N yes September 2015 April 2016 M N yesSeptember 2015April 2016MN Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. 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For browser-based versions of this data sheet, refer to the left-hand navigation. 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。TI の販売条件ti.com お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated Copyright © 2023, Texas Instruments Incorporated table for stability.