JAJS873L March   2000  – December 2023 LP2982

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Output Pulldown
      6. 6.3.6 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Recommended Capacitor Types
        1. 7.1.1.1 Recommended Capacitors for the Legacy Chip
        2. 7.1.1.2 Recommended Capacitors for the New Chip
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Noise Bypass Capacitor (CBYPASS)
      4. 7.1.4 Reverse Current
      5. 7.1.5 Power Dissipation (PD)
      6. 7.1.6 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 ON/ OFF Input Operation
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス命名規則
    2. 10.2 サード・パーティ製品に関する免責事項
    3. 10.3 ドキュメントのサポート
      1. 10.3.1 関連資料
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 サポート・リソース
    6. 10.6 商標
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 %
Legacy chip (A grade) –1.0 1.0
New chip –0.5 0.5
1 mA < IL < 50 mA Legacy chip (standard grade) –2 2
Legacy chip (A grade) –1.5 1.5
New chip –0.5 0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5
Legacy chip (A grade) –2 2
New chip –1 1
ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V < VIN < 16 V Legacy chip 0.007 0.014 %/V
New chip 0.002 0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032
New chip 0.002 0.032
ΔVOUT(ΔILOAD) Load regulation 1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V New chip 0.1 0.5 %/A
VDO Dropout voltage(1) IOUT = 0 mA Legacy chip 1 3 mV
New chip 1 2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 5
New chip 3
IOUT = 1 mA Legacy chip 7 10
New chip 11.5 14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 15
New chip 17
IOUT = 10 mA Legacy chip 40 60
New chip 98 115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 90
New chip 148
IOUT = 50 mA Legacy chip 120 150
New chip 120 145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 225
New chip 184
IOUT = 80 mA Legacy chip 180 225
New chip 150 165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 325
New chip 204
IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA
New chip 69 95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125
New chip 123
IOUT = 1 mA Legacy chip 80 110
New chip 78 110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170
New chip 140
IOUT = 10 mA Legacy chip 140 220 µA
New chip 175 210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 460
New chip 250
IOUT = 50 mA Legacy chip 375 600 µA
New chip 380 440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1200 µA
New chip 650 µA
IOUT = 80 mA Legacy chip 525 750 µA
New chip 575 720 µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1400 µA
900 µA
VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 µA
New chip 1.25 1.75 µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.1 2 µA
New chip 1.12 2.75 µA
VUVLO+ Rising bias supply UVLO VIN rising, –40°C ≤ TJ ≤ 125°C New chip 2.2 2.4 V
VUVLO- Falling bias supply UVLO VIN falling, –40°C ≤ TJ ≤ 125°C 1.9 V
VUVLO(HYST) UVLO hysteresis –40°C ≤ TJ ≤ 125°C 0.130 V
IO(MAX) Short Output Current RL = 0 Ω (steady state) Legacy chip 150 mA
New chip 150 mA
IO(PK) Peak Output Current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 100 150 mA
New chip 100 150 mA
VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V
New chip 0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15
New chip 0.15
High = Output ON Legacy chip 1.4
New chip 0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6
New chip 1.6
ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA
New chip 0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA
New chip –0.9 µA
VON/OFF = 5 V Legacy chip 5 µA
New chip 0.011 µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 15 µA
New chip 2.20 µA
ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB
New chip 78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA 45 dB
Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA Legacy chip 30 µVRMS
New chip 30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA 50
Tsd+ Thermal shutdown threshold Shutdown, temperature increasing New chip 170 °C
Tsd- Reset, temperature decreasing 150
(1) Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.