JAJSS37 データシート | TI.com

JAJSS37K November 2001 – December 2023 LP2992

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

NGD|6
- MPDS393
DBV|5
- MPDS018T

サーマルパッド・メカニカル・データ

発注情報

6.3.3 Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (I_CL). I_CL is listed in the LP2992 マイクロパワー、250mA、低ノイズ、超低ドロップアウトレギュレータ、SOT-23 および WSON パッケージ、超低 ESR の出力コンデンサで使用するように設計 LP2992 マイクロパワー、250mA、低ノイズ、超低ドロップアウトレギュレータ、SOT-23 および WSON パッケージ、超低 ESR の出力コンデンサで使用するように設計 LP2992 マイクロパワー、250mA、低ノイズ、超低ドロップアウトレギュレータ、SOT-23 および WSON パッケージ、超低 ESR の出力コンデンサで使用するように設計特長特長アプリケーションアプリケーション概要概要 Table of Contents Table of Contents Pin Configuration and Functions Pin Configuration and Functions Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Electrical Characteristics Electrical Characteristics Thermal Information Thermal Information Typical Characteristics Typical Characteristics Detailed Description Detailed Description Overview Overview Functional Block Diagram Functional Block Diagram Feature Description Feature Description Output Enable Output Enable Dropout Voltage Dropout Voltage Current Limit Current Limit Undervoltage Lockout (UVLO) Undervoltage Lockout (UVLO) Output Pulldown Output Pulldown Thermal Shutdown Thermal Shutdown Device Functional Modes Device Functional Modes Device Functional Mode Comparison Device Functional Mode Comparison Normal Operation Normal Operation Dropout Operation Dropout Operation Disabled Disabled Application and Implementation Application and Implementation Application Information Application Information Estimating Junction Temperature Estimating Junction Temperature Input and Output Capacitor Requirements Input and Output Capacitor Requirements Noise Bypass Capacitor (CBYPASS) Noise Bypass Capacitor (CBYPASS) Power Dissipation (PD) Power Dissipation (PD) Recommended Capacitor Types Recommended Capacitor Types Reverse Current Reverse Current Typical Application Typical Application Design Requirements Design Requirements Detailed Design Procedure Detailed Design Procedure ON/OFF Operation ON/OFF Operation Application Curves Application Curves Power Supply Recommendations Power Supply Recommendations Layout Layout Layout Guidelines Layout Guidelines Layout Examples Layout Examples Device and Documentation Support Device and Documentation Support Device Nomenclature Device Nomenclature Documentation Support Documentation Support Related Documentation Related Documentation Receiving Notification of Documentation Updates Receiving Notification of Documentation Updates サポート・リソースサポート・リソース Trademarks Trademarks 静電気放電に関する注意事項静電気放電に関する注意事項用語集用語集 Revision History Revision History Revision History Revision History Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information 重要なお知らせと免責事項重要なお知らせと免責事項 LP2992 マイクロパワー、250mA、低ノイズ、超低ドロップアウトレギュレータ、SOT-23 および WSON パッケージ、超低 ESR の出力コンデンサで使用するように設計 LP2992 マイクロパワー、250mA、低ノイズ、超低ドロップアウトレギュレータ、SOT-23 および WSON パッケージ、超低 ESR の出力コンデンサで使用するように設計特長 K 文書全体にわたって表、図、相互参照の採番方法を更新 yes I 上端に TI デザイン用のナビゲーションアイコンを追加 yes H 「製品情報」および「ESD 定格」表、「ピンの構成と機能」セクション、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加、「熱に関する値」とピンの名前を更新 yes K 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes K ドキュメントに M3 デバイスを追加 yes VIN 範囲 (新チップ)：2.5V～16V VOUT 範囲 (新チップ)： 1.2V～5.0V (固定、100mV ステップ) VOUT 精度： ±1% (A グレードの従来チップ) ±1.5% (標準グレードの従来チップ) ±0.5% (新チップのみ) 負荷および温度の全範囲にわたって ±1% の出力精度 (新チップの場合) 出力電流：最大 250 mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：875μA (ILOAD = 250 mA の場合) シャットダウン電流： 0.01μA (標準値) (従来チップ) 1.12μA (標準値) (新チップ) 低ノイズ：30μVRMS (10nF のバイパス・コンデンサを使用した場合) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作高い PSRR：1kHz で 70dB、1MHz で 40dB 動作時接合部温度：-40℃～125℃ パッケージ：5 ピン SOT-23 (DBV) 特長 K 文書全体にわたって表、図、相互参照の採番方法を更新 yes I 上端に TI デザイン用のナビゲーションアイコンを追加 yes H 「製品情報」および「ESD 定格」表、「ピンの構成と機能」セクション、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加、「熱に関する値」とピンの名前を更新 yes K 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes K ドキュメントに M3 デバイスを追加 yes K 文書全体にわたって表、図、相互参照の採番方法を更新 yes I 上端に TI デザイン用のナビゲーションアイコンを追加 yes H 「製品情報」および「ESD 定格」表、「ピンの構成と機能」セクション、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加、「熱に関する値」とピンの名前を更新 yes K 文書全体にわたって表、図、相互参照の採番方法を更新 yes K文書全体にわたって表、図、相互参照の採番方法を更新yes I 上端に TI デザイン用のナビゲーションアイコンを追加 yes I上端に TI デザイン用のナビゲーションアイコンを追加yes H 「製品情報」および「ESD 定格」表、「ピンの構成と機能」セクション、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加、「熱に関する値」とピンの名前を更新 yes H「製品情報」および「ESD 定格」表、「ピンの構成と機能」セクション、「機能説明」セクション、「デバイスの機能モード」セクション、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションを追加、「熱に関する値」とピンの名前を更新 yes K 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes K ドキュメントに M3 デバイスを追加 yes K 現在のファミリのフォーマットに合わせてドキュメント全体を変更 yes K現在のファミリのフォーマットに合わせてドキュメント全体を変更yes K ドキュメントに M3 デバイスを追加 yes Kドキュメントに M3 デバイスを追加yes VIN 範囲 (新チップ)：2.5V～16V VOUT 範囲 (新チップ)： 1.2V～5.0V (固定、100mV ステップ) VOUT 精度： ±1% (A グレードの従来チップ) ±1.5% (標準グレードの従来チップ) ±0.5% (新チップのみ) 負荷および温度の全範囲にわたって ±1% の出力精度 (新チップの場合) 出力電流：最大 250 mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：875μA (ILOAD = 250 mA の場合) シャットダウン電流： 0.01μA (標準値) (従来チップ) 1.12μA (標準値) (新チップ) 低ノイズ：30μVRMS (10nF のバイパス・コンデンサを使用した場合) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作高い PSRR：1kHz で 70dB、1MHz で 40dB 動作時接合部温度：-40℃～125℃ パッケージ：5 ピン SOT-23 (DBV) VIN 範囲 (新チップ)：2.5V～16V VOUT 範囲 (新チップ)： 1.2V～5.0V (固定、100mV ステップ) VOUT 精度： ±1% (A グレードの従来チップ) ±1.5% (標準グレードの従来チップ) ±0.5% (新チップのみ) 負荷および温度の全範囲にわたって ±1% の出力精度 (新チップの場合) 出力電流：最大 250 mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：875μA (ILOAD = 250 mA の場合) シャットダウン電流： 0.01μA (標準値) (従来チップ) 1.12μA (標準値) (新チップ) 低ノイズ：30μVRMS (10nF のバイパス・コンデンサを使用した場合) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作高い PSRR：1kHz で 70dB、1MHz で 40dB 動作時接合部温度：-40℃～125℃ パッケージ：5 ピン SOT-23 (DBV) VIN 範囲 (新チップ)：2.5V～16V VOUT 範囲 (新チップ)： 1.2V～5.0V (固定、100mV ステップ) VOUT 精度： ±1% (A グレードの従来チップ) ±1.5% (標準グレードの従来チップ) ±0.5% (新チップのみ) 負荷および温度の全範囲にわたって ±1% の出力精度 (新チップの場合) 出力電流：最大 250 mA 低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合) 低い IQ (新チップ)：875μA (ILOAD = 250 mA の場合) シャットダウン電流： 0.01μA (標準値) (従来チップ) 1.12μA (標準値) (新チップ) 低ノイズ：30μVRMS (10nF のバイパス・コンデンサを使用した場合) 出力電流制限および過熱保護 2.2µF のセラミック・コンデンサで安定動作高い PSRR：1kHz で 70dB、1MHz で 40dB 動作時接合部温度：-40℃～125℃ パッケージ：5 ピン SOT-23 (DBV) VIN 範囲 (新チップ)：2.5V～16VINVOUT 範囲 (新チップ)： 1.2V～5.0V (固定、100mV ステップ) OUT 1.2V～5.0V (固定、100mV ステップ) 1.2V～5.0V (固定、100mV ステップ)VOUT 精度： ±1% (A グレードの従来チップ) ±1.5% (標準グレードの従来チップ) ±0.5% (新チップのみ) OUT ±1% (A グレードの従来チップ) ±1.5% (標準グレードの従来チップ) ±0.5% (新チップのみ) ±1% (A グレードの従来チップ)±1.5% (標準グレードの従来チップ)±0.5% (新チップのみ)負荷および温度の全範囲にわたって ±1% の出力精度 (新チップの場合)出力電流：最大 250 mA低い IQ (新チップ)：69μA (ILOAD = 0 mA の場合)QLOAD低い IQ (新チップ)：875μA (ILOAD = 250 mA の場合)QLOADシャットダウン電流： 0.01μA (標準値) (従来チップ) 1.12μA (標準値) (新チップ) 0.01μA (標準値) (従来チップ) 1.12μA (標準値) (新チップ) 0.01μA (標準値) (従来チップ)1.12μA (標準値) (新チップ)低ノイズ：30μVRMS (10nF のバイパス・コンデンサを使用した場合)RMS出力電流制限および過熱保護2.2µF のセラミック・コンデンサで安定動作高い PSRR：1kHz で 70dB、1MHz で 40dB動作時接合部温度：-40℃～125℃パッケージ：5 ピン SOT-23 (DBV) アプリケーション洗濯機 / 乾燥機陸上移動無線アクティブ・アンテナ・システムの mMIMO コードレス電動工具モータ・ドライブおよび制御基板アプリケーション洗濯機 / 乾燥機陸上移動無線アクティブ・アンテナ・システムの mMIMO コードレス電動工具モータ・ドライブおよび制御基板洗濯機 / 乾燥機陸上移動無線アクティブ・アンテナ・システムの mMIMO コードレス電動工具モータ・ドライブおよび制御基板洗濯機 / 乾燥機陸上移動無線アクティブ・アンテナ・システムの mMIMO コードレス電動工具モータ・ドライブおよび制御基板洗濯機 / 乾燥機洗濯機 / 乾燥機陸上移動無線陸上移動無線アクティブ・アンテナ・システムの mMIMO アクティブ・アンテナ・システムの mMIMO コードレス電動工具コードレス電動工具モータ・ドライブおよび制御基板モータ・ドライブおよび制御基板概要 K 文書全体にわたって表、図、相互参照の採番方法を更新 yes J 「概略回路」図のコンデンサから具体的な値を削除 yes G ナショナルセミコンダクターのデータシートのレイアウトを TI 形式に変更 yes LP2992 は、固定出力で入力範囲の広い、低ノイズ、低ドロップアウトの電圧レギュレータで、2.5V～16V の入力電圧範囲に対応し、最大 250mA の負荷電流を供給できます。LP2992 は、1.2V～5.0V の出力範囲をサポートしています (新チップの場合)。さらに、LP2992 (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。 30μVRMS (10nF のバイパス・コンデンサを使用) の低い出力ノイズと、1kHz で 70dB、1MHz で 40dB を上回る広い帯域幅の PSRR 性能により、上流側 DC/DC コンバータのスイッチング周波数を低くすることができ、さらに、レギュレータ後のフィルタ処理を最小限に抑えることができます。内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 LP2992 は、5 ピン、2.9mm × 2.8mm の SOT-23 (DBV) パッケージで供給されます。パッケージ情報部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm 詳細については、を参照してください。パッケージサイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。新チップのドロップアウト電圧と温度との関係代表的なアプリケーション回路概要 K 文書全体にわたって表、図、相互参照の採番方法を更新 yes J 「概略回路」図のコンデンサから具体的な値を削除 yes G ナショナルセミコンダクターのデータシートのレイアウトを TI 形式に変更 yes K 文書全体にわたって表、図、相互参照の採番方法を更新 yes J 「概略回路」図のコンデンサから具体的な値を削除 yes G ナショナルセミコンダクターのデータシートのレイアウトを TI 形式に変更 yes K 文書全体にわたって表、図、相互参照の採番方法を更新 yes K文書全体にわたって表、図、相互参照の採番方法を更新yes J 「概略回路」図のコンデンサから具体的な値を削除 yes J「概略回路」図のコンデンサから具体的な値を削除 yes G ナショナルセミコンダクターのデータシートのレイアウトを TI 形式に変更 yes Gナショナルセミコンダクターのデータシートのレイアウトを TI 形式に変更yes LP2992 は、固定出力で入力範囲の広い、低ノイズ、低ドロップアウトの電圧レギュレータで、2.5V～16V の入力電圧範囲に対応し、最大 250mA の負荷電流を供給できます。LP2992 は、1.2V～5.0V の出力範囲をサポートしています (新チップの場合)。さらに、LP2992 (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。 30μVRMS (10nF のバイパス・コンデンサを使用) の低い出力ノイズと、1kHz で 70dB、1MHz で 40dB を上回る広い帯域幅の PSRR 性能により、上流側 DC/DC コンバータのスイッチング周波数を低くすることができ、さらに、レギュレータ後のフィルタ処理を最小限に抑えることができます。内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 LP2992 は、5 ピン、2.9mm × 2.8mm の SOT-23 (DBV) パッケージで供給されます。パッケージ情報部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm 詳細については、を参照してください。パッケージサイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。新チップのドロップアウト電圧と温度との関係代表的なアプリケーション回路 LP2992 は、固定出力で入力範囲の広い、低ノイズ、低ドロップアウトの電圧レギュレータで、2.5V～16V の入力電圧範囲に対応し、最大 250mA の負荷電流を供給できます。LP2992 は、1.2V～5.0V の出力範囲をサポートしています (新チップの場合)。さらに、LP2992 (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。 30μVRMS (10nF のバイパス・コンデンサを使用) の低い出力ノイズと、1kHz で 70dB、1MHz で 40dB を上回る広い帯域幅の PSRR 性能により、上流側 DC/DC コンバータのスイッチング周波数を低くすることができ、さらに、レギュレータ後のフィルタ処理を最小限に抑えることができます。内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。 LP2992 は、5 ピン、2.9mm × 2.8mm の SOT-23 (DBV) パッケージで供給されます。パッケージ情報部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm 詳細については、を参照してください。パッケージサイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。新チップのドロップアウト電圧と温度との関係代表的なアプリケーション回路 LP2992 は、固定出力で入力範囲の広い、低ノイズ、低ドロップアウトの電圧レギュレータで、2.5V～16V の入力電圧範囲に対応し、最大 250mA の負荷電流を供給できます。LP2992 は、1.2V～5.0V の出力範囲をサポートしています (新チップの場合)。さらに、LP2992 (新チップ) は、負荷および温度の全範囲にわたって 1% の出力精度を備えており、低電圧マイクロコントローラ (MCU) およびプロセッサのニーズを満たすことができます。30μVRMS (10nF のバイパス・コンデンサを使用) の低い出力ノイズと、1kHz で 70dB、1MHz で 40dB を上回る広い帯域幅の PSRR 性能により、上流側 DC/DC コンバータのスイッチング周波数を低くすることができ、さらに、レギュレータ後のフィルタ処理を最小限に抑えることができます。RMS内部ソフトスタート時間および電流制限保護により、スタートアップ時の突入電流が減少し、入力静電容量を最小化しました。過電流および過熱保護などの一般的な保護機能を備えています。LP2992 は、5 ピン、2.9mm × 2.8mm の SOT-23 (DBV) パッケージで供給されます。パッケージ情報部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm パッケージ情報部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm 部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB 部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE パッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB 部品番号パッケージ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTE #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/DEVINFONOTEパッケージサイズ #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB #GUID-70FD80FD-48DF-40D6-9121-8E5306950668/LI_MC3_S55_XXB LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm LP2992 DBV (SOT-23、5) 2.9mm × 2.8mm LP2992DBV (SOT-23、5)2.9mm × 2.8mm WSON (6) 3.29 mm×2.92 mm WSON (6)3.29 mm×2.92 mm 詳細については、を参照してください。パッケージサイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。詳細については、を参照してください。パッケージサイズ (長さ×幅) は公称値であり、該当する場合はピンも含まれます。新チップのドロップアウト電圧と温度との関係代表的なアプリケーション回路新チップのドロップアウト電圧と温度との関係新チップのドロップアウト電圧と温度との関係代表的なアプリケーション回路代表的なアプリケーション回路 Table of Contents Table of Contents Pin Configuration and Functions DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. Pin Configuration and Functions DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. DBV Package, 5-Pin SOT-23 (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. DBV Package, 5-Pin SOT-23 (Top View) DBV Package, 5-Pin SOT-23 (Top View) DBV Package,5-Pin SOT-23(Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. Pin Functions PIN TYPE DESCRIPTION NAME NO. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. PIN TYPE DESCRIPTION NAME NO. PIN TYPE DESCRIPTION PINTYPEDESCRIPTION NAME NO. NAMENO. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. BYPASS 4 I/O BYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. BYPASS4I/OBYPASS pin to achieve low noise performance. Connecting an external capacitor between BYPASS pin and ground reduces reference voltage noise. See the section for more information. GND 2 — Ground GND2—Ground ON/OFF 3 I Enable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused. ON/OFF OFF3IEnable pin for the LDO. Driving the ON/OFF pin high enables the device. Driving this pin low disables the device. High and low thresholds are listed in the table. Tie this pin to VIN if unused.OFFIN VIN 1 I Input supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VIN IN1IInput supply pin. Use a capacitor with a value of 1 µF or larger from this pin to ground. See for more information. VOUT 5 O Output of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information. VOUT OUT5OOutput of the regulator. Use a capacitor with a value of 2.2 µF or larger from this pin to ground#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22. See the section for more information.#GUID-4B59F65F-C257-4FEB-8513-DEF1CBC7316F/GUID-810D06AB-FEAA-4AFC-AF3D-594915300F22 The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. The nominal output capacitance must be greater than 1 μF. Throughout this document, the nominal derating on these capacitors is 50%. Make sure that the effective capacitance at the pin is greater than 1 μF. Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Current Maximum output Internally limited A Temperature Operating junction, TJ –55 150 °C –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VOUT Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 VBYPASS Bypass voltage 1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 250 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability. Electrical Characteristics K Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip) yes specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 New chip –1 1 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 Legacy chip (A grade) –3.5 3.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 Legacy chip (A grade) –4.5 4.5 New chip –1 1 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V New chip 2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 New chip 2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 75 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 50 mA Legacy chip 350 600 New chip 380 440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 New chip 650 IOUT = 150 mA Legacy chip 850 1500 New chip 765 890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 New chip 1060 IOUT = 250 mA Legacy Chip 1500 2300 New Chip 875 1010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 New Chip 1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 New chip 3 IOUT = 1 mA Legacy chip 5 9 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 New chip 17 IOUT = 50 mA Legacy chip 100 125 New chip 120 145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 New chip 184 IOUT = 150 mA Legacy chip 260 325 New chip 180 198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 New chip 254 IOUT = 250 mA Legacy chip 450 575 New chip 225 260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 New chip 340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA New chip –0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA New chip 300 350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 New chip 375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB New chip 78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS New chip 30 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Typical Characteristics CIN = 1 µF, COUT = 4.7 µF, VIN = VOUT(NOM) + 1 V, TA = 25°C, ON/OFF pin is tied to the IN pin (unless otherwise noted) V_OUT vs Temperature for Legacy Chip V_OUT vs Temperature for New Chip VIN = 4.3 V, VOUT = 3.3 V (for new chip) Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 6 V Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 16 V Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for New Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for New Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for New Chip I_GND vs Load and Temperature for Legacy Chip I_GND vs Load and Temperature for New Chip Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for New Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Current Maximum output Internally limited A Temperature Operating junction, TJ –55 150 °C –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Current Maximum output Internally limited A Temperature Operating junction, TJ –55 150 °C –65 150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Current Maximum output Internally limited A Temperature Operating junction, TJ –55 150 °C –65 150 over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378541/A_7DD4C9AC_94E6_46C4_97E4_3064DB517237_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2 MIN MAX UNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Current Maximum output Internally limited A Temperature Operating junction, TJ –55 150 °C –65 150 MIN MAX UNIT MIN MAX UNIT MINMAXUNIT VIN Continuous input voltage range (for legacy chip) –0.3 16 V Continuous input voltage range (for new chip) –0.3 18 VOUT Output voltage range (for legacy chip) –0.3 9 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 ON/OFF pin voltage range (for new chip) –0.3 18 Current Maximum output Internally limited A Temperature Operating junction, TJ –55 150 °C –65 150 VIN Continuous input voltage range (for legacy chip) –0.3 16 V VIN IN Continuous input voltage range (for legacy chip)–0.316V Continuous input voltage range (for new chip) –0.3 18 Continuous input voltage range (for new chip) –0.318 VOUT Output voltage range (for legacy chip) –0.3 9 VOUT OUTOutput voltage range (for legacy chip)–0.39 Output voltage range (for new chip) –0.3 VIN + 0.3 or 9 (whichever is smaller) Output voltage range (for new chip) –0.3VIN + 0.3 or 9 (whichever is smaller)IN VBYPASS BYPASS pin voltage range (for new chip) –0.3 3 VBYPASS BYPASSBYPASS pin voltage range (for new chip)–0.33 VON/OFF ON/OFF pin voltage range (for legacy chip) –0.3 16 VON/OFF ON/OFF OFFON/OFF pin voltage range (for legacy chip)OFF–0.316 ON/OFF pin voltage range (for new chip) –0.3 18 ON/OFF pin voltage range (for new chip)OFF–0.318 Current Maximum output Internally limited A CurrentMaximum outputInternally limitedA Temperature Operating junction, TJ –55 150 °C TemperatureOperating junction, TJ J–55150°C –65 150 –65150 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltages with respect to GND. Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.All voltages with respect to GND. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. ESD Ratings VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 VALUE (Legacy Chip) VALUE (New Chip) UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 VALUE (Legacy Chip) VALUE (New Chip) UNIT VALUE (Legacy Chip) VALUE (New Chip) UNIT VALUE (Legacy Chip)VALUE (New Chip)UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM ±2000 ±3000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/HBM_COMM±2000±3000V Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM ±500 ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281564/CDM_COMM±500±1000 JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VOUT Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 VBYPASS Bypass voltage 1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 250 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability. Recommended Operating Conditions MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VOUT Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 VBYPASS Bypass voltage 1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 250 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 TJ Operating junction temperature –40 125 °C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability. MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VOUT Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 VBYPASS Bypass voltage 1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 250 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 TJ Operating junction temperature –40 125 °C MIN NOM MAX UNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VOUT Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 VBYPASS Bypass voltage 1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 250 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 TJ Operating junction temperature –40 125 °C MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VIN Supply input voltage (for legacy chip) 2.2 16 V Supply input voltage (for new chip) 2.5 16 VOUT Output voltage (for legacy chip) 1.2 10.0 Output voltage (for new chip) 1.2 5.0 VBYPASS Bypass voltage 1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN Enable voltage (for new chip) 0 16 IOUT Output current 0 250 mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 TJ Operating junction temperature –40 125 °C VIN Supply input voltage (for legacy chip) 2.2 16 V VIN INSupply input voltage (for legacy chip)2.216V Supply input voltage (for new chip) 2.5 16 Supply input voltage (for new chip)2.516 VOUT Output voltage (for legacy chip) 1.2 10.0 VOUT OUTOutput voltage (for legacy chip)1.210.0 Output voltage (for new chip) 1.2 5.0 Output voltage (for new chip)1.25.0 VBYPASS Bypass voltage 1.2 VBYPASS BYPASSBypass voltage1.2 VON/OFF Enable voltage (for legacy chip) 0 VIN VON/OFF ON/OFF OFFEnable voltage (for legacy chip)0VIN IN Enable voltage (for new chip) 0 16 Enable voltage (for new chip)016 IOUT Output current 0 250 mA IOUT OUTOutput current0250mA CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 Input capacitor 1 μF CIN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 IN#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25Input capacitor1μF COUT Output capacitor (for legacy chip) 2.2 4.7 μF COUT OUTOutput capacitor (for legacy chip)2.24.7μF Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 1 2.2 200 Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A25 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000281560/ROCFOOTER2_TPS7A2512.2200 TJ Operating junction temperature –40 125 °C TJ JOperating junction temperature–40125°C All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability. All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 μF minimum for stability. Electrical Characteristics K Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip) yes specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 New chip –1 1 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 Legacy chip (A grade) –3.5 3.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 Legacy chip (A grade) –4.5 4.5 New chip –1 1 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V New chip 2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 New chip 2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 75 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 50 mA Legacy chip 350 600 New chip 380 440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 New chip 650 IOUT = 150 mA Legacy chip 850 1500 New chip 765 890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 New chip 1060 IOUT = 250 mA Legacy Chip 1500 2300 New Chip 875 1010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 New Chip 1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 New chip 3 IOUT = 1 mA Legacy chip 5 9 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 New chip 17 IOUT = 50 mA Legacy chip 100 125 New chip 120 145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 New chip 184 IOUT = 150 mA Legacy chip 260 325 New chip 180 198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 New chip 254 IOUT = 250 mA Legacy chip 450 575 New chip 225 260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 New chip 340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA New chip –0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA New chip 300 350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 New chip 375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB New chip 78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS New chip 30 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Electrical Characteristics K Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip) yes K Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip) yes K Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip) yes KUpdated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)yes specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 New chip –1 1 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 Legacy chip (A grade) –3.5 3.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 Legacy chip (A grade) –4.5 4.5 New chip –1 1 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V New chip 2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 New chip 2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 75 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 50 mA Legacy chip 350 600 New chip 380 440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 New chip 650 IOUT = 150 mA Legacy chip 850 1500 New chip 765 890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 New chip 1060 IOUT = 250 mA Legacy Chip 1500 2300 New Chip 875 1010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 New Chip 1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 New chip 3 IOUT = 1 mA Legacy chip 5 9 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 New chip 17 IOUT = 50 mA Legacy chip 100 125 New chip 120 145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 New chip 184 IOUT = 150 mA Legacy chip 260 325 New chip 180 198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 New chip 254 IOUT = 250 mA Legacy chip 450 575 New chip 225 260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 New chip 340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA New chip –0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA New chip 300 350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 New chip 375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB New chip 78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS New chip 30 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 New chip –1 1 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 Legacy chip (A grade) –3.5 3.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 Legacy chip (A grade) –4.5 4.5 New chip –1 1 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V New chip 2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 New chip 2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 75 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 50 mA Legacy chip 350 600 New chip 380 440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 New chip 650 IOUT = 150 mA Legacy chip 850 1500 New chip 765 890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 New chip 1060 IOUT = 250 mA Legacy Chip 1500 2300 New Chip 875 1010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 New Chip 1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 New chip 3 IOUT = 1 mA Legacy chip 5 9 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 New chip 17 IOUT = 50 mA Legacy chip 100 125 New chip 120 145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 New chip 184 IOUT = 150 mA Legacy chip 260 325 New chip 180 198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 New chip 254 IOUT = 250 mA Legacy chip 450 575 New chip 225 260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 New chip 340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA New chip –0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA New chip 300 350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 New chip 375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB New chip 78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS New chip 30 specified at TJ = 25°C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)JINOUT(nom)OUTON/OFFINOUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 New chip –1 1 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 Legacy chip (A grade) –3.5 3.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 Legacy chip (A grade) –4.5 4.5 New chip –1 1 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V New chip 2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 New chip 2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 75 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 50 mA Legacy chip 350 600 New chip 380 440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 New chip 650 IOUT = 150 mA Legacy chip 850 1500 New chip 765 890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 New chip 1060 IOUT = 250 mA Legacy Chip 1500 2300 New Chip 875 1010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 New Chip 1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 New chip 3 IOUT = 1 mA Legacy chip 5 9 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 New chip 17 IOUT = 50 mA Legacy chip 100 125 New chip 120 145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 New chip 184 IOUT = 150 mA Legacy chip 260 325 New chip 180 198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 New chip 254 IOUT = 250 mA Legacy chip 450 575 New chip 225 260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 New chip 340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA New chip –0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA New chip 300 350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 New chip 375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB New chip 78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS New chip 30 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Legacy chip (A grade) –1.0 1.0 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 Legacy chip (A grade) –1.5 1.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 Legacy chip (A grade) –2.5 2.5 New chip –1 1 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 Legacy chip (A grade) –3.5 3.5 New chip –0.5 0.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 Legacy chip (A grade) –4.5 4.5 New chip –1 1 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V New chip 0.002 0.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 New chip 0.002 0.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V New chip 2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 New chip 2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA New chip 69 95 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 New chip 123 IOUT = 1 mA Legacy chip 75 110 New chip 78 110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 New chip 140 IOUT = 50 mA Legacy chip 350 600 New chip 380 440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 New chip 650 IOUT = 150 mA Legacy chip 850 1500 New chip 765 890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 New chip 1060 IOUT = 250 mA Legacy Chip 1500 2300 New Chip 875 1010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 New Chip 1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 New chip 1.25 1.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 New chip 1.12 2.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV New chip 1 2.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 New chip 3 IOUT = 1 mA Legacy chip 5 9 New chip 11.5 14 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 New chip 17 IOUT = 50 mA Legacy chip 100 125 New chip 120 145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 New chip 184 IOUT = 150 mA Legacy chip 260 325 New chip 180 198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 New chip 254 IOUT = 250 mA Legacy chip 450 575 New chip 225 260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 New chip 340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V New chip 0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 New chip 0.15 High = Output ON Legacy chip 1.4 New chip 0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 New chip 1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA New chip –0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA New chip 0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA New chip 300 350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 New chip 375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB New chip 78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS New chip 30 Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Output voltage tolerance IL = 1 mA Legacy chip (standard grade) –1.5 1.5 % Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)∆VOUT Updated Absolute Maximum Ratings, Recommended Operating Conditions, Electrical Characteristics and Thermal Information for M3-suffix(new chip)OUTOutput voltage tolerance IL = 1 mALLegacy chip (standard grade)–1.51.5% Legacy chip (A grade) –1.0 1.0 Legacy chip (A grade)–1.01.0 New chip –0.5 0.5 New chip–0.50.5 1 mA ≤ IL ≤ 50 mA Legacy chip (standard grade) –2.5 2.5 1 mA ≤ IL ≤ 50 mALLegacy chip (standard grade)–2.52.5 Legacy chip (A grade) –1.5 1.5 Legacy chip (A grade)–1.51.5 New chip –0.5 0.5 New chip–0.50.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –3.5 3.5 1 mA ≤ IL ≤ 50 mA, –40°C ≤ TJ ≤ 125°CLJ Legacy chip (standard grade)–3.53.5 Legacy chip (A grade) –2.5 2.5 Legacy chip (A grade)–2.52.5 New chip –1 1 New chip–11 1 mA ≤ IL ≤ 250 mA Legacy chip (standard grade) –4 4 1 mA ≤ IL ≤ 250 mALLegacy chip (standard grade)–44 Legacy chip (A grade) –3.5 3.5 Legacy chip (A grade)–3.53.5 New chip –0.5 0.5 New chip–0.50.5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip (standard grade) –5 5 1 mA ≤ IL ≤ 250 mA, –40°C ≤ TJ ≤ 125°CLJ Legacy chip (standard grade)–55 Legacy chip (A grade) –4.5 4.5 Legacy chip (A grade)–4.54.5 New chip –1 1 New chip–11 ΔVOUT(ΔVIN) Line regulation VO(NOM) + 1 V ≤ VIN ≤ 16 V Legacy chip 0.007 0.014 %/V ΔVOUT(ΔVIN) OUT(ΔVIN)Line regulationVO(NOM) + 1 V ≤ VIN ≤ 16 VO(NOM)INLegacy chip0.0070.014%/V New chip 0.002 0.014 New chip0.0020.014 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.007 0.032 VO(NOM) + 1 V ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°CO(NOM)INJLegacy chip0.0070.032 New chip 0.002 0.032 New chip0.0020.032 VIN(MIN) Minimum input voltage required to maintain output regulation Legacy chip 2.05 V VIN(MIN) IN(MIN)Minimum input voltage required to maintain output regulationLegacy chip2.05V New chip 2.05 New chip2.05 Minimum input voltage required to maintain output regulation –40°C ≤ TJ ≤ 125°C Legacy chip 2.2 Minimum input voltage required to maintain output regulation–40°C ≤ TJ ≤ 125°CJ Legacy chip2.2 New chip 2.35 New chip2.35 IGND GND pin current IOUT = 0 mA Legacy chip 65 95 µA IGND GND GND pin currentIOUT = 0 mAOUTLegacy chip6595µA New chip 69 95 New chip6995 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 125 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip125 New chip 123 New chip123 IOUT = 1 mA Legacy chip 75 110 IOUT = 1 mAOUTLegacy chip75110 New chip 78 110 New chip78110 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 170 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip170 New chip 140 New chip140 IOUT = 50 mA Legacy chip 350 600 IOUT = 50 mAOUTLegacy chip350600 New chip 380 440 New chip380440 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 1000 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip1000 New chip 650 New chip650 IOUT = 150 mA Legacy chip 850 1500 IOUT = 150 mAOUTLegacy chip8501500 New chip 765 890 New chip765890 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 2500 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip2500 New chip 1060 New chip1060 IOUT = 250 mA Legacy Chip 1500 2300 IOUT = 250 mAOUTLegacy Chip15002300 New Chip 875 1010 New Chip8751010 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy Chip 4000 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy Chip4000 New Chip 1200 New Chip1200 VON/OFF < 0.3 V, VIN = 16 V Legacy chip 0.01 0.8 VON/OFF < 0.3 V, VIN = 16 VON/OFFINLegacy chip0.010.8 New chip 1.25 1.75 New chip1.251.75 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.05 2 VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°CON/OFFINJ Legacy chip0.052 New chip 1.12 2.75 New chip1.122.75 VDO Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 IOUT = 0 mA Legacy chip 0.5 2.5 mV VDO DODropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377227/A_0F649DB2_778E_4F95_91D7_D1C72312B08D_LP298X_LP2992_300MM_AA_ELECTRICAL_CHARACTERISTICS_3_SHEET2_FOOTER1IOUT = 0 mAOUTLegacy chip0.52.5mV New chip 1 2.75 New chip12.75 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 4 IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip4 New chip 3 New chip3 IOUT = 1 mA Legacy chip 5 9 IOUT = 1 mAOUTLegacy chip59 New chip 11.5 14 New chip11.514 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 12 IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip12 New chip 17 New chip17 IOUT = 50 mA Legacy chip 100 125 IOUT = 50 mAOUTLegacy chip100125 New chip 120 145 New chip120145 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 180 IOUT = 50 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip180 New chip 184 New chip184 IOUT = 150 mA Legacy chip 260 325 IOUT = 150 mAOUTLegacy chip260325 New chip 180 198 New chip180198 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 470 IOUT = 150 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip470 New chip 254 New chip254 IOUT = 250 mA Legacy chip 450 575 IOUT = 250 mAOUTLegacy chip450575 New chip 225 260 New chip225260 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°C Legacy chip 850 IOUT = 250 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip850 New chip 340 New chip340 VON/OFF ON/OFF input voltage Low = Output OFF Legacy chip 0.55 V VON/OFF ON/OFF OFFON/OFF input voltageOFFLow = Output OFFLegacy chip0.55V New chip 0.72 New chip0.72 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 0.15 Low = Output OFF, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C OUTINJLegacy chip0.15 New chip 0.15 New chip0.15 High = Output ON Legacy chip 1.4 High = Output ONLegacy chip1.4 New chip 0.85 New chip0.85 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip 1.6 High = Output ON, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C OUTINJLegacy chip1.6 New chip 1.6 New chip1.6 ION/OFF ON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C Legacy chip –2 µA ION/OFF ON/OFF OFFON/OFF input current VON/OFF = 0 V, VOUT + 1 ≤ VIN ≤ 16 V, –40°C ≤ TJ ≤ 125°C ON/OFFOUTINJ Legacy chip–2µA New chip –0.9 New chip–0.9 ION/OFF ON/OFF input current VON/OFF = 0 V Legacy chip 0.01 µA ION/OFF ON/OFF OFFON/OFF input currentVON/OFF = 0 VON/OFFLegacy chip0.01µA New chip 0.42 New chip0.42 IO(PK) Peak output current VOUT ≥ VO(NOM) –5% (steady state) Legacy chip 300 350 mA IO(PK)Peak output current VOUT ≥ VO(NOM) –5% (steady state) OUTO(NOM)Legacy chip300350mA New chip 300 350 New chip300350 IO(SC) Short output current RL = 0 Ω (steady state) Legacy chip 400 IO(SC) O(SC)Short output currentRL = 0 Ω (steady state)LLegacy chip400 New chip 375 New chip375 ΔVO/ΔVIN Ripple rejection f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF Legacy chip 45 dB ΔVO/ΔVIN OINRipple rejectionf = 1 kHz, CBYPASS = 10 nF, COUT = 10 µFBYPASSOUTLegacy chip45dB New chip 78 New chip78 Vn Output noise voltage Bandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V Legacy chip 30 µVRMS Vn nOutput noise voltageBandwidth = 300 Hz to 50 kHz, CBYPASS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 VBYPASSOUT OUTLegacy chip30µVRMS VRMS New chip 30 New chip30 Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices. Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.DODOINOUT(nom) Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT DBV (SOT23-5) DBV (SOT23-5) 5 PINS 5 PINS THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-AE290909-62ED-46D9-A60A-07170B3AEFC6Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7ANew Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7A #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378395/GUID-E8E18319-511D-4D08-BFF0-A43759CEAA7AUNIT DBV (SOT23-5) DBV (SOT23-5) DBV (SOT23-5)DBV (SOT23-5) 5 PINS 5 PINS 5 PINS5 PINS RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W RθJA Junction-to-ambient thermal resistance 169.7 178.6 °C/W RθJA θJAJunction-to-ambient thermal resistance169.7178.6°C/W RθJC(top) Junction-to-case (top) thermal resistance 122.6 77.9 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance122.677.9°C/W RθJB Junction-to-board thermal resistance 29.9 47.2 °C/W RθJB θJBJunction-to-board thermal resistance29.947.2°C/W ψJT Junction-to-top characterization parameter 16.7 15.9 °C/W ψJT JTJunction-to-top characterization parameter16.715.9°C/W ψJB Junction-to-board characterization parameter 29.4 46.9 °C/W ψJB JBJunction-to-board characterization parameter29.446.9°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal MetricsThermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the Impact of board layout on LDO thermal performance application report. Impact of board layout on LDO thermal performance Impact of board layout on LDO thermal performance Typical Characteristics CIN = 1 µF, COUT = 4.7 µF, VIN = VOUT(NOM) + 1 V, TA = 25°C, ON/OFF pin is tied to the IN pin (unless otherwise noted) V_OUT vs Temperature for Legacy Chip V_OUT vs Temperature for New Chip VIN = 4.3 V, VOUT = 3.3 V (for new chip) Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 6 V Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 16 V Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for New Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for New Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for New Chip I_GND vs Load and Temperature for Legacy Chip I_GND vs Load and Temperature for New Chip Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for New Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Typical Characteristics CIN = 1 µF, COUT = 4.7 µF, VIN = VOUT(NOM) + 1 V, TA = 25°C, ON/OFF pin is tied to the IN pin (unless otherwise noted) V_OUT vs Temperature for Legacy Chip V_OUT vs Temperature for New Chip VIN = 4.3 V, VOUT = 3.3 V (for new chip) Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 6 V Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 16 V Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for New Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for New Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for New Chip I_GND vs Load and Temperature for Legacy Chip I_GND vs Load and Temperature for New Chip Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for New Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF CIN = 1 µF, COUT = 4.7 µF, VIN = VOUT(NOM) + 1 V, TA = 25°C, ON/OFF pin is tied to the IN pin (unless otherwise noted) V_OUT vs Temperature for Legacy Chip V_OUT vs Temperature for New Chip VIN = 4.3 V, VOUT = 3.3 V (for new chip) Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 6 V Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 16 V Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for New Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for New Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for New Chip I_GND vs Load and Temperature for Legacy Chip I_GND vs Load and Temperature for New Chip Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for New Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF CIN = 1 µF, COUT = 4.7 µF, VIN = VOUT(NOM) + 1 V, TA = 25°C, ON/OFF pin is tied to the IN pin (unless otherwise noted)INOUTINOUT(NOM)AOFF V_OUT vs Temperature for Legacy Chip V_OUT vs Temperature for New Chip VIN = 4.3 V, VOUT = 3.3 V (for new chip) Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 6 V Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 16 V Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for New Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for New Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for New Chip I_GND vs Load and Temperature for Legacy Chip I_GND vs Load and Temperature for New Chip Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for New Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF V_OUT vs Temperature for Legacy Chip V_OUT vs Temperature for Legacy ChipOUT V_OUT vs Temperature for New Chip VIN = 4.3 V, VOUT = 3.3 V (for new chip) V_OUT vs Temperature for New ChipOUT VIN = 4.3 V, VOUT = 3.3 V (for new chip) VIN = 4.3 V, VOUT = 3.3 V (for new chip) VIN = 4.3 V, VOUT = 3.3 V (for new chip) VIN = 4.3 V, VOUT = 3.3 V (for new chip) VIN = 4.3 V, VOUT = 3.3 V (for new chip) VIN = 4.3 V, VOUT = 3.3 V (for new chip)INOUT Short-Circuit Current for Legacy Chip Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 6 V Short-Circuit Current vs Time for New Chip VIN = 6 V VIN = 6 V VIN = 6 V VIN = 6 V VIN = 6 V VIN = 6 VIN Short-Circuit Current for Legacy Chip Short-Circuit Current for Legacy Chip Short-Circuit Current vs Time for New Chip VIN = 16 V Short-Circuit Current vs Time for New Chip VIN = 16 V VIN = 16 V VIN = 16 V VIN = 16 V VIN = 16 V VIN = 16 VIN Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for Legacy Chip Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) Short-Circuit Current vs Output Voltage for New Chip VOUT = 3.3 (for new chip) VOUT = 3.3 (for new chip) VOUT = 3.3 (for new chip) VOUT = 3.3 (for new chip) VOUT = 3.3 (for new chip) VOUT = 3.3 (for new chip)OUT Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nFINOUTOUTBYP Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF Ripple Rejection vs Frequency for New Chip VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nF VIN = 3.7 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 0 nFINOUTOUTBYP Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for Legacy Chip Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF Ripple Rejection vs Frequency for New Chip VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nF VIN = 5 V, VOUT = 3.3 V, COUT = 10 μF, CBYP = 10 nFINOUTOUTBYP Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Impedance vs Frequency for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip Output Noise Density vs Frequency for New Chip Output Noise Density for Legacy Chip Output Noise Density for Legacy Chip Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA Output Noise Density vs Frequency for New Chip VOUT = 3.3 V, IOUT = 150 mA VOUT = 3.3 V, IOUT = 150 mA VOUT = 3.3 V, IOUT = 150 mA VOUT = 3.3 V, IOUT = 150 mA VOUT = 3.3 V, IOUT = 150 mA VOUT = 3.3 V, IOUT = 150 mAOUTOUT GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for Legacy Chip GND Pin vs Load Current for New Chip GND Pin vs Load Current for New Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for Legacy Chip Dropout Voltage vs Temperature for New Chip Dropout Voltage vs Temperature for New Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for Legacy Chip Input Current vs Input Voltage for New Chip Input Current vs Input Voltage for New Chip I_GND vs Load and Temperature for Legacy Chip I_GND vs Load and Temperature for Legacy ChipGND I_GND vs Load and Temperature for New Chip I_GND vs Load and Temperature for New ChipGND Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for Legacy Chip Short-Circuit Current vs Temperature for New Chip Short-Circuit Current vs Temperature for New Chip Load Transient Response for Legacy Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient for New Chip dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for New Chip dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for Legacy Chip Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs Load Transient Response for New Chip VOUT = 3.3 V, dI/dt = 1 A/μs VOUT = 3.3 V, dI/dt = 1 A/μs VOUT = 3.3 V, dI/dt = 1 A/μs VOUT = 3.3 V, dI/dt = 1 A/μs VOUT = 3.3 V, dI/dt = 1 A/μs VOUT = 3.3 V, dI/dt = 1 A/μsOUT Line Transient Response for Legacy Chip Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μOUTBYPINOUT Line Transient Response for Legacy Chip Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μOUTBYPINOUT Line Transient Response for Legacy Chip Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μOUTBYPINOUT Line Transient Response for Legacy Chip Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 10 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μOUTBYPINOUT Turn-on Time for Legacy Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for New Chip COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μFOUT Turn-on Time for Legacy Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for New Chip COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μFOUT Detailed Description Overview The LP2991 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and nonportable applications. The LP2991 has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 250 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. Functional Block Diagram Feature Description Output Enable The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. The device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage. Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Undervoltage Lockout (UVLO) The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Output Pulldown Q Added Output Pulldown section yes The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis resets (turns on) the device when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Device Functional Modes Device Functional Mode Comparison #GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 shows the conditions that lead to the different modes of operation. See for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Detailed Description Overview The LP2991 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and nonportable applications. The LP2991 has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 250 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. Overview The LP2991 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and nonportable applications. The LP2991 has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 250 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. The LP2991 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and nonportable applications. The LP2991 has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 250 mA of continuous load current. This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. The LP2991 is a fixed-output, low-noise, high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for both portable and nonportable applications. The LP2991 has an output tolerance of 1% across line, load, and temperature variation (for the new chip) and is capable of delivering 250 mA of continuous load current.This device features integrated overcurrent protection, thermal shutdown, output enable, and internal output pulldown and has a built-in soft-start mechanism for controlled inrush current. This device delivers excellent line and load transient performance. The operating ambient temperature range of the device is –40°C to 125°C. Functional Block Diagram Functional Block Diagram Feature Description Output Enable The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. The device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage. Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Undervoltage Lockout (UVLO) The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Output Pulldown Q Added Output Pulldown section yes The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis resets (turns on) the device when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Feature Description Output Enable The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. The device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage. Output Enable The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. The device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage. The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device. The device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage. The ON/OFF pin for the device is an active-high pin. The output voltage is enabled when the voltage of the ON/OFF pin is greater than the high-level input voltage of the ON/OFF pin and disabled with the ON/OFF pin voltage is less than the low-level input voltage of the ON/OFF pin. If independent control of the output voltage is not needed, connect the ON/OFF pin to the input of the device.OFFOFFOFFOFFOFFOFFThe device has an internal pulldown circuit that activates when the device is disabled by pulling the ON/OFF pin voltage lower than the low-level input voltage of the ON/OFF pin, to actively discharge the output voltage.OFFOFF Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device. Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well.DOINOUTRATEDRATEDOUT For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. The following equation calculates the RDS(ON) of the device.DS(ON)DS(ON) Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table. The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note. shows a diagram of the current limit. Current Limit The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a brick-wall scheme. In a high-load current fault, the brick-wall scheme limits the output current to the current limit (ICL). ICL is listed in the table.CLCL The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note.INOUTCL Know Your Limits Know Your Limits shows a diagram of the current limit. Current Limit Current Limit Undervoltage Lockout (UVLO) The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Undervoltage Lockout (UVLO) The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input drops during turn on, the UVLO has hysteresis as specified in the table. Output Pulldown Q Added Output Pulldown section yes The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Output Pulldown Q Added Output Pulldown section yes Q Added Output Pulldown section yes Q Added Output Pulldown section yes QAdded Output Pulldown sectionOutput Pulldownyes The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. The new chip has an output pulldown circuit. The output pulldown activates in the following conditions: When the device is disabled (VON/OFF < VON/OFF(LOW)) If 1.0 V < VIN < VUVLO When the device is disabled (VON/OFF < VON/OFF(LOW))ON/OFF OFFON/OFF(LOW)OFFIf 1.0 V < VIN < VUVLO INUVLODo not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can cause damage to the device. See the section for more details. Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis resets (turns on) the device when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Thermal Shutdown The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis resets (turns on) the device when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis resets (turns on) the device when the temperature falls to TSD(reset) (typical). The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes. For reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. The device contains a thermal shutdown protection circuit to disable the device when the junction temperature (TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis resets (turns on) the device when the temperature falls to TSD(reset) (typical).JSD(shutdown)SD(reset)The thermal time-constant of the semiconductor die is fairly short, thus the device can cycle on and off when thermal shutdown is reached until power dissipation is reduced. Power dissipation during start up can be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output capacitors. Under some conditions, the thermal shutdown protection disables the device before start up completes.INOUTFor reliable operation, limit the junction temperature to the maximum listed in the table. Operation above this maximum temperature causes the device to exceed operational specifications. Although the internal protection circuitry of the device is designed to protect against thermal overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability. Device Functional Modes Device Functional Mode Comparison #GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 shows the conditions that lead to the different modes of operation. See for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Device Functional Modes Device Functional Mode Comparison #GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 shows the conditions that lead to the different modes of operation. See for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Device Functional Mode Comparison #GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 shows the conditions that lead to the different modes of operation. See for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) #GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 shows the conditions that lead to the different modes of operation. See for parameter values. Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) #GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 shows the conditions that lead to the different modes of operation. See for parameter values.#GUID-70BA9930-3149-4B61-AADC-A2AA26491D15/X3048 Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Device Functional Mode Comparison OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) OPERATING MODE PARAMETER VIN VON/OFF IOUT TJ OPERATING MODE PARAMETER OPERATING MODEPARAMETER VIN VON/OFF IOUT TJ VIN INVON/OFF ON/OFF OFFIOUT OUTTJ J Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Normal operation VIN > VOUT(nom) + VDO and VIN > VIN(min) VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Normal operationVIN > VOUT(nom) + VDO and VIN > VIN(min) INOUT(nom)DOININ(min)VON/OFF > VON/OFF(HI) ON/OFF OFFON/OFF(HI)OFFIOUT < IOUT(max) OUTOUT(max)TJ < TSD(shutdown) JSD(shutdown) Dropout operation VIN(min) < VIN < VOUT(nom) + VDO VON/OFF > VON/OFF(HI) IOUT < IOUT(max) TJ < TSD(shutdown) Dropout operationVIN(min) < VIN < VOUT(nom) + VDO IN(min)INOUT(nom)DOVON/OFF > VON/OFF(HI) ON/OFF OFFON/OFF(HI)OFFIOUT < IOUT(max) OUTOUT(max)TJ < TSD(shutdown) JSD(shutdown) Disabled (any true condition disables the device) VIN < VUVLO VON/OFF < VON/OFF(LOW) Not applicable TJ > TSD(shutdown) Disabled (any true condition disables the device)VIN < VUVLO INUVLOVON/OFF < VON/OFF(LOW) ON/OFF OFFON/OFF(LOW)OFFNot applicableTJ > TSD(shutdown) JSD(shutdown) Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold Normal Operation The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The device regulates to the nominal output voltage when the following conditions are met: The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO) The output current is less than the current limit (IOUT < ICL) The device junction temperature is less than the thermal shutdown temperature (TJ < TSD) The ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling threshold The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)OUT(nom)DOThe output current is less than the current limit (IOUT < ICL)OUTCLThe device junction temperature is less than the thermal shutdown temperature (TJ < TSD)JSDThe ON/OFF voltage has previously exceeded the ON/OFF rising threshold voltage and has not yet decreased to less than the enable falling thresholdOFFOFF Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations. When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region. If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage tracks the input voltage. During this mode, the transient performance of the device becomes significantly degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load transients in dropout can result in large output-voltage deviations.When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO, directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time while the device pulls the pass transistor back into the linear region.INOUT(NOM)DOnotOUT(NOM)DO Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. Disabled The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground. The output of the device can be shutdown by forcing the voltage of the ON/OFF pin to less than the maximum ON/OFF pin low-level input voltage (see the table). When disabled, the pass transistor is turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.OFFOFF Application and Implementation 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 Application Information Estimating Junction Temperature Q Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Input and Output Capacitor Requirements Q Added Input and Output Capacitor Requirements section no Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the table for stability. Noise Bypass Capacitor (C_BYPASS) Q Added start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) section no The LP2992 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose. Power Dissipation (P_D) Q Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. Recommended Capacitor Types Q Added Recommended Capacitor Types section no The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in account for an effective capacitance of approximately 50% of the nominal value. Reverse Current Q Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Typical Application shows the standard usage of the LP2992 as a low-dropout regulator. LP2992 Typical Application Design Requirements Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. Optional BYPASS capacitor for low-noise operation. Detailed Design Procedure ON/OFF Operation Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. Application Curves Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Application and Implementation 以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。以下のアプリケーション情報は、TI の製品仕様に含まれるものではなく、TI ではその正確性または完全性を保証いたしません。個々の目的に対する製品の適合性については、お客様の責任で判断していただくことになります。お客様は自身の設計実装を検証しテストすることで、システムの機能を確認する必要があります。 Application Information Estimating Junction Temperature Q Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Input and Output Capacitor Requirements Q Added Input and Output Capacitor Requirements section no Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the table for stability. Noise Bypass Capacitor (C_BYPASS) Q Added start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) section no The LP2992 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose. Power Dissipation (P_D) Q Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. Recommended Capacitor Types Q Added Recommended Capacitor Types section no The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in account for an effective capacitance of approximately 50% of the nominal value. Reverse Current Q Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Application Information Estimating Junction Temperature Q Added Estimating Junction Temperature section no The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Estimating Junction Temperature Q Added Estimating Junction Temperature section no Q Added Estimating Junction Temperature section no Q Added Estimating Junction Temperature section no QAdded Estimating Junction Temperature sectionEstimating Junction Temperatureno The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature. TJ = TT + ψJT × PD where: PD is the dissipated power TT is the temperature at the center-top of the device package TJ = TB + ψJB × PD where: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi metrics are determined to be significantly independent of the copper area available for heat-spreading. lists the primary thermal metrics, which are the junction-to-top characterization parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface temperature 1 mm from the device package (TB) to calculate the junction temperature.JTJBJJTTJBBTJ = TT + ψJT × PD JTJTDwhere: PD is the dissipated power TT is the temperature at the center-top of the device package PD is the dissipated powerDTT is the temperature at the center-top of the device packageTTJ = TB + ψJB × PD JBJBDwhere: TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edge TB is the PCB surface temperature measured 1 mm from the device package and centered on the package edgeBFor detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package Thermal Metrics application note. Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal Metrics Input and Output Capacitor Requirements Q Added Input and Output Capacitor Requirements section no Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the table for stability. Input and Output Capacitor Requirements Q Added Input and Output Capacitor Requirements section no Q Added Input and Output Capacitor Requirements section no Q Added Input and Output Capacitor Requirements section no QAdded Input and Output Capacitor Requirements sectionInput and Output Capacitor Requirementsno Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the table for stability. Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source. Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the table for stability. Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load or line transients are anticipated or if the device is located several inches from the input power source.Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor within the range specified in the table for stability. Noise Bypass Capacitor (C_BYPASS) Q Added start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) section no The LP2992 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose. Noise Bypass Capacitor (C_BYPASS)BYPASS Q Added start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) section no Q Added start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) section no Q Added start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) section no QAdded start-up behavior discussion to Noise Bypass Capacitor (CBYPASS) sectionNoise Bypass Capacitor (CBYPASS)BYPASSno The LP2992 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose. The LP2992 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. Use a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose. The LP2992 allows for low-noise performance with the use of a bypass capacitor that is connected to the internal band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is biased in the microampere range and, thus, cannot be loaded significantly, otherwise, the output (and, correspondingly, the output of the regulator) changes. Thus, for best output accuracy, dc leakage current through CBYPASS must be minimized as much as possible and must never exceed 100 nA. The CBYPASS capacitor also impacts the start-up behavior of the regulator. Inrush current and start-up time increase with larger bypass capacitor values. BYPASSBYPASSUse a 10-nF capacitor for CBYPASS. Ceramic and film capacitors are good choices for this purpose.BYPASS Power Dissipation (P_D) Q Added Power Dissipation (PD) section no Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. Power Dissipation (P_D)D Q Added Power Dissipation (PD) section no Q Added Power Dissipation (PD) section no Q Added Power Dissipation (PD) section no QAdded Power Dissipation (PD) sectionPower Dissipation (PD)Dno Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress. To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD). PD = (VIN – VOUT) × IOUT Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation. For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA). TJ = TA + (RθJA × PD) Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance. Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few or no other heat-generating devices that cause added thermal stress.To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. The following equation calculates power dissipation (PD).DPD = (VIN – VOUT) × IOUT DINOUTOUTPower dissipation can be minimized, and therefore greater efficiency can be achieved, by correct selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage required for correct output regulation.For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an array of plated vias that conduct heat to additional copper planes for increased heat dissipation.The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. According to the following equation, power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA).AθJAA TJ = TA + (RθJA × PD) JAθJADThermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The junction-to-ambient thermal resistance listed in table is determined by the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.θJA Recommended Capacitor Types Q Added Recommended Capacitor Types section no The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in account for an effective capacitance of approximately 50% of the nominal value. Recommended Capacitor Types Q Added Recommended Capacitor Types section no Q Added Recommended Capacitor Types section no Q Added Recommended Capacitor Types section no QAdded Recommended Capacitor Types sectionRecommended Capacitor Typesno The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in account for an effective capacitance of approximately 50% of the nominal value. The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in account for an effective capacitance of approximately 50% of the nominal value. The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance.Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and temperature. Generally, expect the effective capacitance to decrease by as much as 50%. The input and output capacitors listed in account for an effective capacitance of approximately 50% of the nominal value. Reverse Current Q Added Reverse Current section no Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Reverse Current Q Added Reverse Current section no Q Added Reverse Current section no Q Added Reverse Current section no QAdded Reverse Current sectionReverse Currentno Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device. Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V. If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the long-term reliability of the device.Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT ≤ VIN + 0.3 V.OUTIN If the device has a large COUT and the input supply collapses with little or no load current The output is biased when the input supply is not established The output is biased above the input supply If the device has a large COUT and the input supply collapses with little or no load currentOUTThe output is biased when the input supply is not establishedThe output is biased above the input supplyIf reverse current flow is expected in the application, use external protection to protect the device. Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation is anticipated. shows one approach for protecting the device. Example Circuit for Reverse Current Protection Using a Schottky Diode Example Circuit for Reverse Current Protection Using a Schottky Diode Typical Application shows the standard usage of the LP2992 as a low-dropout regulator. LP2992 Typical Application Design Requirements Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. Optional BYPASS capacitor for low-noise operation. Detailed Design Procedure ON/OFF Operation Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. Application Curves Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Typical Application shows the standard usage of the LP2992 as a low-dropout regulator. LP2992 Typical Application shows the standard usage of the LP2992 as a low-dropout regulator. LP2992 Typical Application shows the standard usage of the LP2992 as a low-dropout regulator. LP2992 Typical Application LP2992 Typical Application Design Requirements Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. Optional BYPASS capacitor for low-noise operation. Design Requirements Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. Optional BYPASS capacitor for low-noise operation. Minimum COUT value for stability (can be increased without limit for improved stability and transient response) ON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used. Optional BYPASS capacitor for low-noise operation. Minimum COUT value for stability (can be increased without limit for improved stability and transient response)OUTON/OFF must be actively terminated. Connect to VIN if shutdown feature is not used.OFFINOptional BYPASS capacitor for low-noise operation. Detailed Design Procedure ON/OFF Operation Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. Detailed Design Procedure ON/OFF Operation Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. ON/OFF OperationOFF Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes Q Changed LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation section yes QChanged LOW and HIGH pin voltages and deleted slew rate discussion from ON/OFF Operation sectionON/OFF OperationOFFyes The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected. The LP2992 allows for a shutdown mode using the ON/OFF pin. Driving the pin LOW (≤ 0.4 V) turns the device OFF; conversely, a HIGH (≥ 1.2 V) turns the device ON. If the shutdown feature is not used, connect ON/OFF to the input so that the regulator is on at all times. For proper operation, do not leave ON/OFF unconnected.OFFOFFOFF Application Curves Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Application Curves Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Load Transient Response for Legacy Chip Load Transient Response for Legacy Chip Load Transient for New Chip dI/dt = 1 A/μ Load Transient for New Chip dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ Load Transient Response for Legacy Chip Load Transient Response for Legacy Chip Load Transient Response for New Chip dI/dt = 1 A/μ Load Transient Response for New Chip dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ dI/dt = 1 A/μ Line Transient Response for Legacy Chip Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 1 mA, dV/dt = 1 V/μOUTBYPINOUT Line Transient Response for Legacy Chip Line Transient Response for Legacy Chip Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ Line Transient Response for New Chip VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μ VOUT = 3.3 V, CBYP = 0 nF, ΔVIN = 1 V, IOUT = 150 mA, dV/dt = 1 V/μOUTBYPINOUT Turn-on Time for Legacy Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip Turn-on Time for New Chip Turn-on Time for Legacy Chip Turn-on Time for Legacy Chip Turn-on Time for New Chip COUT = 4.7 μF Turn-on Time for New Chip COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μF COUT = 4.7 μFOUT Power Supply Recommendations A power supply can be used at the input voltage within the ranges given in the Recommended Operating Conditions table. Use bypass capacitors as described in the section. Power Supply Recommendations A power supply can be used at the input voltage within the ranges given in the Recommended Operating Conditions table. Use bypass capacitors as described in the section. A power supply can be used at the input voltage within the ranges given in the Recommended Operating Conditions table. Use bypass capacitors as described in the section. A power supply can be used at the input voltage within the ranges given in the Recommended Operating Conditions table. Use bypass capacitors as described in the section. Recommended Operating Conditions Recommended Operating Conditions Recommended Operating Conditions Layout Layout Guidelines Bypass the input pin to ground with a bypass capacitor. The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. Layout Examples Layout Diagram Layout Layout Guidelines Bypass the input pin to ground with a bypass capacitor. The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. Layout Guidelines Bypass the input pin to ground with a bypass capacitor. The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. Bypass the input pin to ground with a bypass capacitor. The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. Bypass the input pin to ground with a bypass capacitor. The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system. For operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. Bypass the input pin to ground with a bypass capacitor.The optimum placement of the bypass capacitor is closest to the VIN of the device and GND of the system. Care must be taken to minimize the loop area formed by the bypass capacitor connection, the VIN pin, and the GND pin of the system.ININFor operation at full-rated load, use wide trace lengths to eliminate IR drop and heat dissipation. Layout Examples Layout Diagram Layout Examples Layout Diagram Layout Diagram Layout Diagram Layout Diagram Device and Documentation Support Device Nomenclature K Added Device Nomenclature section yes Available Options PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Documentation Support Related Documentation I Added additional related document links yes For related documentation see the following: Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Texas Instruments, Using New Thermal Metrics , application note Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note Receiving Notification of Documentation Updates J Added Receiving Notification of Documentation Updates yes To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. サポート・リソーステキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。 Trademarks 静電気放電に関する注意事項この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。用語集テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。 Device and Documentation Support Device Nomenclature K Added Device Nomenclature section yes Available Options PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Device Nomenclature K Added Device Nomenclature section yes K Added Device Nomenclature section yes K Added Device Nomenclature section yes KAdded Device Nomenclature sectionDevice Nomenclatureyes Available Options PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Available Options PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Available Options PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. Available Options PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF VOUT PRODUCT#GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AF #GUID-4DD0F4C2-A81C-4202-92B9-9D076DA7F342/GUID-A9556556-CDAF-490B-987C-C66DDE0A13AFVOUT OUT LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. LP2992-xxyyyz Legacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. LP2992-xxyyyz Legacy chip xxyyyzLegacy chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel.xxyyyz LP2992-xxyyyzM3 New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology. LP2992-xxyyyzM3 New chip xxyyyzM3 M3New chip xx is the nominal output voltage (for example, 33 = 3.3 V; 50 = 5.0 V). yyy is the package designator. z is the package quantity. R is for large quantity reel, T is for small quantity reel. M3 is a suffix designator for newer chip redesigns, fabricated on the latest TI process technology.xxyyyzM3 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com.www.ti.com Documentation Support Related Documentation I Added additional related document links yes For related documentation see the following: Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Texas Instruments, Using New Thermal Metrics , application note Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note Documentation Support Related Documentation I Added additional related document links yes For related documentation see the following: Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Texas Instruments, Using New Thermal Metrics , application note Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note Related Documentation I Added additional related document links yes I Added additional related document links yes I Added additional related document links yes IAdded additional related document links yes For related documentation see the following: Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Texas Instruments, Using New Thermal Metrics , application note Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note For related documentation see the following: Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Texas Instruments, Using New Thermal Metrics , application note Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note For related documentation see the following: Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Texas Instruments, Using New Thermal Metrics , application note Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note Texas Instruments, AN-1187 Leadless Leadframe Package (LLP) , application note AN-1187 Leadless Leadframe Package (LLP) AN-1187 Leadless Leadframe Package (LLP)Texas Instruments, Semiconductor and IC Package Thermal Metrics , application note Semiconductor and IC Package Thermal Metrics Semiconductor and IC Package Thermal MetricsTexas Instruments, Using New Thermal Metrics , application note Using New Thermal Metrics Using New Thermal MetricsTexas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs , application note Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Receiving Notification of Documentation Updates J Added Receiving Notification of Documentation Updates yes To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Receiving Notification of Documentation Updates J Added Receiving Notification of Documentation Updates yes J Added Receiving Notification of Documentation Updates yes J Added Receiving Notification of Documentation Updates yes JAdded Receiving Notification of Documentation Updates Receiving Notification of Documentation Updatesyes To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.Alert me サポート・リソーステキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。サポート・リソーステキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。リンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。テキサス・インスツルメンツ E2E サポート・フォーラムは、エンジニアが検証済みの回答と設計に関するヒントをエキスパートから迅速かつ直接得ることができる場所です。既存の回答を検索したり、独自の質問をしたりすることで、設計で必要な支援を迅速に得ることができます。テキサス・インスツルメンツ E2E サポート・フォーラムテキサス・インスツルメンツ E2Eリンクされているコンテンツは、各寄稿者により「現状のまま」提供されるものです。これらはテキサス・インスツルメンツの仕様を構成するものではなく、必ずしもテキサス・インスツルメンツの見解を反映したものではありません。テキサス・インスツルメンツの使用条件を参照してください。使用条件 Trademarks Trademarks 静電気放電に関する注意事項この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。静電気放電に関する注意事項この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。この IC は、ESD によって破損する可能性があります。テキサス・インスツルメンツは、IC を取り扱う際には常に適切な注意を払うことを推奨します。正しい取り扱いおよび設置手順に従わない場合、デバイスを破損するおそれがあります。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。 ESD による破損は、わずかな性能低下からデバイスの完全な故障まで多岐にわたります。精密な IC の場合、パラメータがわずかに変化するだけで公表されている仕様から外れる可能性があるため、破損が発生しやすくなっています。用語集テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。用語集テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。テキサス・インスツルメンツ用語集テキサス・インスツルメンツ用語集この用語集には、用語や略語の一覧および定義が記載されています。 Revision History yes January 2017 December 2023 J K Revision History yes January 2017 December 2023 J K yes January 2017 December 2023 J K yesJanuary 2017December 2023JK Revision History yes November 2015 January 2017 I J Revision History yes November 2015 January 2017 I J yes November 2015 January 2017 I J yesNovember 2015January 2017IJ Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 重要なお知らせと免責事項 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。 TI は、技術データと信頼性データ (データシートを含みます)、設計リソース (リファレンス・デザインを含みます)、アプリケーションや設計に関する各種アドバイス、Web ツール、安全性情報、その他のリソースを、欠陥が存在する可能性のある「現状のまま」提供しており、商品性および特定目的に対する適合性の黙示保証、第三者の知的財産権の非侵害保証を含むいかなる保証も、明示的または黙示的にかかわらず拒否します。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。これらのリソースは、TI 製品を使用する設計の経験を積んだ開発者への提供を意図したものです。(1) お客様のアプリケーションに適した TI 製品の選定、(2) お客様のアプリケーションの設計、検証、試験、(3) お客様のアプリケーションに該当する各種規格や、その他のあらゆる安全性、セキュリティ、規制、または他の要件への確実な適合に関する責任を、お客様のみが単独で負うものとします。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。上記の各種リソースは、予告なく変更される可能性があります。これらのリソースは、リソースで説明されている TI 製品を使用するアプリケーションの開発の目的でのみ、TI はその使用をお客様に許諾します。これらのリソースに関して、他の目的で複製することや掲載することは禁止されています。TI や第三者の知的財産権のライセンスが付与されている訳ではありません。お客様は、これらのリソースを自身で使用した結果発生するあらゆる申し立て、損害、費用、損失、責任について、TI およびその代理人を完全に補償するものとし、TI は一切の責任を拒否します。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。 TI の製品は、TI の販売条件、または ti.com やかかる TI 製品の関連資料などのいずれかを通じて提供する適用可能な条項の下で提供されています。TI がこれらのリソースを提供することは、適用される TI の保証または他の保証の放棄の拡大や変更を意味するものではありません。TI の販売条件ti.com お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE お客様がいかなる追加条項または代替条項を提案した場合でも、TI はそれらに異議を唱え、拒否します。IMPORTANT NOTICE IMPORTANT NOTICE 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2023, Texas Instruments Incorporated 郵送先住所：Texas Instruments, Post Office Box 655303, Dallas, Texas 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The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the device begins to heat up because of the increase in power dissipation. When the device is in brick-wall current limit, the pass transistor dissipates power [(V_IN – V_OUT) × I_CL]. If thermal shutdown is triggered, the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For more information on current limits, see the Know Your Limits application note.

Figure 6-1 shows a diagram of the current limit.

Figure 6-1 Current Limit