SLAS928B March 2013 – November 2016 LP3988-Q1
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The dynamic performance of the LP3988-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP3988-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3988-Q1 device, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP3988-Q1 GND pin using as wide and as short of a copper trace as is practical.
Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions.
The PG pin pullup resistor must be connected to the LP3988-Q1 OUT pin, with the pullup resistor located as close as is practical to the PG pin.