SNVS251J May   2004  – September 2014 LP3990

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Output Capacitor, Recommended Specifications
    7. 6.7 Timing Requirements
    8. 6.8 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Enable (EN)
      2. 7.3.2 Thermal Overload Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
      2. 7.4.2 Minimum Operating Input Voltage (VIN)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Power Dissipation and Device Operation
        2. 8.2.2.2 External Capacitors
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Output Capacitor
        5. 8.2.2.5 No-Load Stability
        6. 8.2.2.6 Capacitor Characteristics
        7. 8.2.2.7 Enable Control
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 DSBGA Mounting
    4. 10.4 DSBGA Light Sensitivity
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP3990 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDO's may degrade the load regulation, PSRR, noise, or transient performance of the LP3990.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3990, and as close as is practical to the package. The ground connections for CIN and COUT should be back to the LP3990 ground pin using as wide, and as short, of a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided. These will add parasitic inductances and resistance that results in inferior performance especially during transient conditions.

A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly recommended. This Ground Plane serves two purposes : 1) Provide a circuit reference plane to assure accuracy, and 2) provides a thermal plane to remove heat from the LP3990 WSON package through thermal vias under the package DAP.

10.2 Layout Examples

layout_TL_PCB_snvs251.gifFigure 17. LP3990 DSBGA Layout
layout_MF_PCB_snvs251.gifFigure 18. LP3990 SOT-23 Layout
layout_SD_PCB_snvs251.gifFigure 19. LP3990 WSON Layout

10.3 DSBGA Mounting

The DSBGA package requires specific mounting techniques, which are detailed in TI Application Note DSBGA Wafer Level Chip Scale PackageSNVA009.

For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device.

10.4 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may affect the operation of the device. Light sources, such as halogen lamps, can affect electrical performance, if placed in close proximity to the device.

Light with wavelengths in the infra-red portion of the spectrum is the most detrimental, and so, fluorescent lighting used inside most buildings, has little or no effect on performance.