SNVS179F February   2003  – September 2015 LP3995

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Input Test Signals
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN)
      2. 8.3.2 Fast Turnoff
      3. 8.3.3 Low Output Noise
      4. 8.3.4 Output Capacitor
      5. 8.3.5 Thermal Overload Protection (TSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 External Capacitors
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 No-Load Stability
        5. 9.2.2.5 Capacitor Characteristics
        6. 9.2.2.6 Noise Bypass Capacitor
        7. 9.2.2.7 Fast Turnoff and Turnon
        8. 9.2.2.8 Power Dissipation
        9. 9.2.2.9 Estimating Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
    3. 11.3 DSBGA Mounting
    4. 11.4 DSBGA Light Sensitivity
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

The dynamic performance of the LP3995 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP3995. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP3995, and as close as is practical to the package. The ground connections for CIN and COUT should be back to the LP3995 ground pin using as wide, and as short, of a copper trace as is practical. Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided. These add parasitic inductances and resistance that result in inferior performance especially during transient conditions.

11.2 Layout Examples

LP3995 dsbga_layout.gif Figure 22. LP3995 DSBGA Layout
LP3995 wson_layout.gif Figure 23. LP3995 WSON Layout

11.3 DSBGA Mounting

The DSBGA package requires specific mounting techniques that are detailed in TI's AN-1112 Application Report (SNVA009). Referring to the section Surface Mount Assembly Considerations, it should be noted that the pad style which must be used with the 5-pin package is NSMD (non-solder mask defined) type.

For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the DSBGA device.

11.4 DSBGA Light Sensitivity

Exposing the DSBGA device to direct sunlight may cause mis-operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device.

The wavelengths that have the most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has little effect on performance. Tests carried out on a DSBGA test board showed a negligible effect on the regulated output voltage when brought within 1 cm of a fluorescent lamp. A deviation of less than 0.1% from nominal output voltage was observed.