JAJSHH1B May   2019  – August 2020 LP5009 , LP5012

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 PWM Control for Each Channel
        1. 8.3.1.1 Independent Color Mixing Per RGB LED Module
        2. 8.3.1.2 Independent Intensity Control Per RGB LED Module
          1. 8.3.1.2.1 Intensity-Control Register Configuration
          2. 8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control
        3. 8.3.1.3 12-Bit, 29-kHz PWM Generator Per Channel
          1. 8.3.1.3.1 PWM Generator
        4. 8.3.1.4 PWM Phase-Shifting
      2. 8.3.2 LED Bank Control
      3. 8.3.3 Current Range Setting
      4. 8.3.4 Automatic Power-Save Mode
      5. 8.3.5 Protection Features
        1. 8.3.5.1 Thermal Shutdown
        2. 8.3.5.2 UVLO
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C Slave Addressing
        5. 8.5.1.5 Control-Register Write Cycle
        6. 8.5.1.6 Control-Register Read Cycle
        7. 8.5.1.7 Auto-Increment Feature
    6. 8.6 Register Maps
      1.      45
      2. 8.6.1  DEVICE_CONFIG0 (Address = 0h) [reset = 0h]
      3. 8.6.2  DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]
      4. 8.6.3  LED_CONFIG0 (Address = 2h) [reset = 00h]
      5. 8.6.4  BANK_BRIGHTNESS (Address = 3h) [reset = FFh]
      6. 8.6.5  BANK_A_COLOR (Address = 4h) [reset = 00h]
      7. 8.6.6  BANK_B_COLOR (Address = 5h) [reset = 00h]
      8. 8.6.7  BANK_C_COLOR (Address = 6h) [reset = 00h]
      9. 8.6.8  LED0_BRIGHTNESS (Address = 7h) [reset = FFh]
      10. 8.6.9  LED1_BRIGHTNESS (Address = 8h) [reset = FFh]
      11. 8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]
      12. 8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]
      13. 8.6.12 OUT0_COLOR (Address = 0Bh) [reset = 00h]
      14. 8.6.13 OUT1_COLOR (Address = 0Ch) [reset = 00h]
      15. 8.6.14 OUT2_COLOR (Address = 0Dh) [reset = 00h]
      16. 8.6.15 OUT3_COLOR (Address = 0Eh) [reset = 00h]
      17. 8.6.16 OUT4_COLOR (Address = 0Fh) [reset = 00h]
      18. 8.6.17 OUT5_COLOR (Address = 10h) [reset = 00h]
      19. 8.6.18 OUT6_COLOR (Address = 11h) [reset = 00h]
      20. 8.6.19 OUT7_COLOR (Address = 12h) [reset = 00h]
      21. 8.6.20 OUT8_COLOR (Address = 13h) [reset = 00h]
      22. 8.6.21 OUT9_COLOR (Address = 14h) [reset = 00h]
      23. 8.6.22 OUT10_COLOR (Address = 15h) [reset = 00h]
      24. 8.6.23 OUT11_COLOR (Address = 16h) [reset = 00h]
      25. 8.6.24 RESET (Address = 17h) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first. Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an acknowledge after each byte has been received.

There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1 indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.

GUID-31D6471D-4A6F-4493-A902-6D7D28FBE8FA-low.gifFigure 8-10 Acknowledge and Not Acknowledge on I2C Bus