The master device sends the slave address (7 bits) and the data direction bit (R/
W = 0).
The slave device sends an acknowledge signal if the slave address is correct.
The master device sends the control register address (8 bits).
The slave device sends an acknowledge signal.
The master device sends the data byte to be written to the addressed register.
The slave device sends an acknowledge signal.
If the master device sends further data bytes, the control register address of the slave is incremented by 1 after the acknowledge signal. To reduce program load time, the device supports address auto incrementation. The register address is incremented after each 8 data bits.
The write cycle ends when the master device creates a stop condition.