The LP5521 is a three-channel LED driver designed to produce variety of lighting effects for mobile devices. A high-efficiency charge pump enables LED driving over full Li-Ion battery voltage range. The device has a program memory for creating variety of lighting sequences. When program memory has been loaded, LP5521 can operate autonomously without processor control allowing power savings.
The device maintains excellent efficiency over a wide operating range by automatically selecting proper charge pump gain based on LED forward voltage requirements and is able to automatically enter power-save mode, when LED outputs are not active and thus lowering current consumption.
Three independent LED channels have accurate programmable current sources and PWM control. Each channel has program memory for creating desired lighting sequences with PWM control.
The LP5521 has a flexible digital interface. Trigger I/O and a 32-kHz clock input allow synchronization between multiple devices. Interrupt output can be used to notify processor, when LED sequence has ended. The LP5521 has four pin selectable I2C-compatible addresses. This allows connecting up to four parallel devices in one I2C-compatible bus. GPO and INT pins can be used as a digital control pin for other devices.
The LP5521 requires only four small, low-cost ceramic capacitors.
Comprehensive application tools are available, including command compiler for easy LED sequence programming.
PART NUMBER | PACKAGE | BODY SIZE |
---|---|---|
LP5521TM | DSBGA (20) | 2.093 mm × 1.733 mm (MAX) |
LP5521YQ | WQFN (24) | 5.00 mm × 4.00 mm (NOM) |
Changes from H Revision (May 2016) to I Revision
Changes from G Revision (September 2014) to H Revision
Changes from F Revision (February 2013) to G Revision
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NUMBER | NAME | ||
1A | B | A | Current source output |
1B | G | A | Current source output |
1C | R | A | Current source output |
1D | SCL | I | I2C Serial interface clock input |
1E | SDA | I/OD | I2C Serial interface data input/output |
2A | VOUT | A | Charge pump output |
2B | ADDR_SEL1 | I | I2C address select input |
2C | ADDR_SEL0 | I | I2C address select input |
2D | GPO | O | General purpose output |
2E | EN | I | Chip enable |
3A | CFLY2N | A | Negative terminal of charge pump fly capacitor 2 |
3B | CFLY1N | A | Negative terminal of charge pump fly capacitor 1 |
3C | GND | G | Ground |
3D | CLK_32K | I | 32-kHz clock input |
3E | INT | OD/O | Interrupt output / General Purpose Output |
4A | CFLY2P | A | Positive terminal of charge pump fly capacitor 2 |
4B | CFLY1P | A | Positive terminal of charge pump fly capacitor 1 |
4C | VDD | P | Power supply pin |
4D | GND | G | Ground |
4E | TRIG | I/OD | Trigger input/output |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NUMBER | NAME | ||
1 | CFLY2P | A | Positive pin of charge pump fly capacitor 2 |
2 | CFLY1P | A | Positive pin of charge pump fly capacitor 1 |
3 | VDD | P | Power supply pin |
4 | GND | G | Ground |
5 | CLK_32K | I | 32-kHz clock input |
6 | INT | OD/O | Interrupt output / General purpose output |
7 | TRIG | I/OD | Trigger input/output |
8 | N/C | ||
9 | N/C | ||
10 | N/C | ||
11 | N/C | ||
12 | N/C | ||
13 | SDA | I/OD | I2C serial interface data input/output |
14 | EN | I | Chip enable |
15 | SCL | I | I2C Serial interface clock input |
16 | GPO | O | General purpose output |
17 | R | A | Current source output |
18 | G | A | Current source output |
19 | B | A | Current source output |
20 | ADDR_SEL0 | I | I2C address select input |
21 | ADDR_SEL1 | I | I2C address select input |
22 | VOUT | A | Charge pump output |
23 | CFLY2N | A | Negative pin of charge pump fly capacitor 2 |
24 | CFLY1N | A | Negative pin of charge pump fly capacitor 1 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
V (VDD , VOUT, R, G, B) | –0.3 | 6 | V | |
Voltage on logic pins | –0.3 | VDD + 0.3 with 6 V maximum | V | |
Continuous power dissipation(4) | Internally Limited | |||
Junction temperature, TJ-MAX | 125 | °C | ||
Maximum lead temperature (soldering) | See(5) | |||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±200 |
MIN | MAX | UNIT | |
---|---|---|---|
VDD | 2.7 | 5.5 | V |
Recommended charge pump load current IOUT | 0 | 100 | mA |
Junction temperature, TJ, | –30 | 125 | °C |
Ambient temperature, TA(3) | –30 | 85 | °C |
THERMAL METRIC(1) | LP5521 | UNIT | ||
---|---|---|---|---|
YFQ (DSBGA) | NJA (WQFN) | |||
20 PINS | 24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 70.7 | 38.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 0.5 | 27.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 12.1 | 15.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.2 | 0.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 12.0 | 15.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | 3.1 | °C/W |
SYMBOL | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
IVDD | Standby supply current | EN = 0 (pin), CHIP_EN = 0 (bit), external 32 kHz clock running or not running | 0.2 | μA | ||
EN = 0 (pin), CHIP_EN = 0 (bit), external 32-kHz clock running or not running, –30°C < TA < 85°C | 2 | |||||
EN = 1 (pin), CHIP_EN = 0 (bit), external 32-kHz clock not running | 1 | μA | ||||
EN = 1 (pin), CHIP_EN = 0 (bit), external 32-kHz clock running | 1.4 | μA | ||||
Normal mode supply current | Charge pump and LED drivers disabled | 0.25 | mA | |||
Charge pump in 1x mode, no load, LED drivers disabled | 0.7 | mA | ||||
Charge pump in 1.5x mode, no load, LED drivers disabled | 1.5 | mA | ||||
Charge pump in 1x mode, no load, LED drivers enabled | 1.2 | mA | ||||
Powersave mode supply current | External 32-kHz clock running | 10 | μA | |||
Internal oscillator running | 0.25 | mA | ||||
ƒOSC | Internal oscillator frequency accuracy | –4% | 4% | |||
–30°C < TA < 85°C | –7% | 7% |
SYMBOL | PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
ROUT | Charge pump output resistance | Gain = 1.5× | 3.5 | Ω | ||
Gain = 1× | 1 | Ω | ||||
fSW | Switching frequency | 1.25 | MHz | |||
–30°C < TA < 85°C | –7% | 7% | ||||
IGND | Ground current | Gain = 1.5× | 1.2 | mA | ||
Gain = 1× | 0.5 | mA | ||||
tON | VOUT turn-on time from charge pump off to 1.5x mode | VDD = 3.6 V, CHIP_EN = H IOUT = 60 mA |
100 | μs | ||
VOUT | Charge pump output voltage | VDD = 3.6 V, no load, Gain = 1.5× | 4.55 | V |
SYMBOL | PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
ILEAKAGE | R, G, B pin leakage current | 0.1 | µA | |||
–30°C < TA < 85°C | 1 | |||||
IMAX | Maximum source current | Outputs R, G, B | 25.5 | mA | ||
IOUT | Accuracy of output current | Output current set to 17.5 mA, VDD = 3.6 V | –4% | 4% | ||
Output current set to 17.5 mA, VDD = 3.6 V, –30°C < TA < 85°C |
–5% | 5% | ||||
IMATCH | Matching(1) | IOUT = 17.5 mA, VDD = 3.6 V | 1% | 2% | ||
fLED | LED PWM switching frequency | PWM_HF = 1 Frequency defined by internal oscillator |
558 | Hz | ||
PWM_HF = 0 Frequency defined by 32-kHz clock (internal or external) |
256 | Hz | ||||
VSAT | Saturation voltage(2) | IOUT set to 17.5 mA | 50 | 100 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
LOGIC INPUT EN | ||||||
VIL | Input low level | 0.5 | V | |||
VIH | Input high level | 1.2 | V | |||
II | Logic input current | –1 | 1 | µA | ||
tDELAY | Input delay (1) | TJ = 25°C | 2 | µs | ||
LOGIC INPUT SCL, SDA, TRIG, CLK_32K | ||||||
VIL | Input low level | 0.2 × V(EN) | V | |||
VIH | Input high level | 0.8 × V(EN) | V | |||
II | Input current | –1 | 1 | µA | ||
ƒCLK_32K | Clock frequency | TJ = 25°C | 32 | kHz | ||
ƒSCL | Clock frequency | 400 | kHz | |||
LOGIC OUTPUT SDA, TRIG, INT | ||||||
IOUT = 3 mA (pullup current), TJ = 25°C |
0.3 | |||||
VOL | Output low level | IOUT = 3 mA (pull-up current) | 0.5 | V | ||
IL | Output leakage current | 1 | µA | |||
LOGIC INPUT ADDR_SEL0, ADDR_SEL1 | ||||||
VIL | Input low level | 0.2 × VDD | V | |||
VIH | Input high level | 0.8 × VDD | V | |||
II | Input current | –1 | 1 | µA | ||
LOGIC OUTPUT GPO, INT (IN GPO STATE) | ||||||
IOUT = 3 mA, TJ = 25°C | 0.3 | |||||
VOL | Output low level | IOUT = 3 mA | 0.5 | V | ||
TJ = 25°C | VDD – 0.3 | |||||
VOH | Output high level | IOUT = –2 mA | VDD – 0.5 | V | ||
IL | Output leakage current | 1 | µA |
MIN | MAX | UNIT | ||
---|---|---|---|---|
ƒSCL | Clock frequency | 400 | kHz | |
1 | Hold time (repeated) START condition | 0.6 | µs | |
2 | Clock low time | 1.3 | µs | |
3 | Clock high time | 600 | ns | |
4 | Setup time for a repeated START condition | 600 | ns | |
5 | Data hold time | 50 | ns | |
6 | Data set-up time | 100 | ns | |
7 | Rise time of SDA and SCL | 20+0.1Cb | 300 | ns |
8 | Fall time of SDA and SCL | 15+0.1Cb | 300 | ns |
9 | Set-up time for STOP condition | 600 | ns | |
10 | Bus-free time between a STOP and a START condition | 1.3 | µs | |
Cb | Capacitive load for each bus line | 10 | 200 | pF |