7.3.1.1 Boost Standby Mode

User can stop the boost converter operation by writing the Enables register bit EN_BOOST low. When EN_BOOST is written high, the converter starts for 10 ms in PFM mode and then goes to PWM mode.

7.3.1.2 Boost Output Voltage Control

User can control the Boost output voltage by boost output 8-bit register.

Figure 11. Boost Output Voltage Control

7.3.1.3 Boost Frequency Control

Register-frequency selections (address 10h). Register default value after reset is 07h.

Table 1. LED Current Level Adjust

Table 2. LED PWM Control

7.3.2.1 PWM Control Timing

PWM frequency can be selected from 3 predefined values: 10 kHz, 20 kHz, and 40 kHz. The frequency is selected with FPWM1 and FPWM0 bits, see Table 3.

Each RGB set has equivalent internal PWM timing between R, G, and B: R has a fixed start time, G has a fixed mid-pulse time, and B has a fixed-pulse end time. PWM start time for each RGB set is different in order to minimize the instantaneous current loading due to the current sink switch on transition. See Figure 12 for details.

Figure 12. Timing Diagram

7.3.3.1 Control of Audio Synchronization

Table 4 describes the controls required for audio synchronization. ALED brightness control through serial interface is not available when audio synchronization is enabled.

7.3.3.2 ALED Driver

The LP55281 device has a single ALED driver. It is a constant current sink with an 8-bit control. ALED driver can be used as a DC current sink or an audio synchronized current sink. Note, that when the audio synchronization function is enabled, the 8-bit current control register has no effect.

ALED driver is enabled when audio synchronization is enabled (EN_SYNC = 1) or when ALED[7:0] control byte has other than 00h value.

Figure 14. ALED Driver

7.3.3.2.1 Adjustment of ALED Driver

Adjustment of the ALED driver current (Register 0Ch) is described in Table 7.

Table 7. ALED Driver Current

ALED[7:0]	DRIVER CURRENT, mA (typical)
0000 0000	0
0000 0001	0.06
0000 0010	0.1
...	...
1111 1101	14.8
1111 1110	14.9
1111 1111	15

With values other than those in Table 7, the current value can be calculated to be (15 mA / 255) × ALED[7:0], where ALED[7:0] is value in decimals.

Figure 15. Principle of LED Connection to ADC

Table 8. LED Multiplexing (Register 12h)

7.3.4.1 LED Test Procedure

An example of LED test sequence is presented here. Note that user can use incremental write sequence on I²C. The test sequence consists of the basic setup and measurement phases for all RGB LEDs and boost voltage.

Basic setup phase for the device:

1. Give reset to LP55281 (by power on, NRST pin or write any data to register 60h)
2. Set the preferred value for RED1 (write 3Fh, 7Fh, BFh or FFh to register 00h)
3. Set the preferred value for GREEN1 (write 3Fh, 7Fh, BFh or FFh to register 01h)
4. Set the preferred value for BLUE1 (write 3Fh, 7Fh, BFh or FFh to register 02h)
5. Set the preferred value for RED2 (write 3Fh, 7Fh, BFh or FFh to register 03h)
6. Set the preferred value for GREEN2 (write 3Fh, 7Fh, BFh or FFh to register 04h)
7. Set the preferred value for BLUE2 (write 3Fh, 7Fh, BFh or FFh to register 05h)
8. Set the preferred value for RED3 (write 3Fh, 7Fh, BFh or FFh to register 06h)
9. Set the preferred value for GREEN3 (write 3Fh, 7Fh, BFh or FFh to register 07h)
10. Set the preferred value for BLUE3 (write 3Fh, 7Fh, BFh or FFh to register 08h)
11. Set the preferred value for RED4 (write 3Fh, 7Fh, BFh or FFh to register 09h)
12. Set the preferred value for GREEN4 (write 3Fh, 7Fh, BFh or FFh to register 0Ah)
13. Set the preferred value for BLUE4 (write 3Fh, 7Fh, BFh or FFh to register 0Bh)
14. Set the preferred value for ALED (write 01h - FFh to register 0Ch)
15. Dummy write: 00h to register 0Dh (Only if the incremental write sequence is used)
16. Dummy write: 00h to register 0Eh (Only if the incremental write sequence is used)
17. Set preferred boost voltage (write 00h - FFh to register 0Fh)
18. Set preferred boost frequency (write 00h - 07h to register 10h, PWM frequency can be anything)
19. Enable boost and RGB drivers (write CFh to register 11h)
20. Wait 20 ms for the device and boost start-up

Measurement phase:

1. Enable LED test and select output (write 1xh to register 12h)
2. Wait for 128 µs
3. Read ADC output (read register 13h)
4. Go to step 1 of measurement phase and define next output to be measured as many times as needed
5. Disable LED test (write 00h to register 12h) or give reset to the device (see step 1 in basic setup phase)

7.3.4.2 LED Test Time Estimation

Assuming the maximum clock frequencies used in SPI or I²C-compatible interfaces, Table 9 predicts the overall test sequence time for the test procedure shown above. This estimation gives the shortest time possible. Incremental write is assumed with I²C. Reset and LED test disable are not included.

7.5.2.1 Interface Bus Overview

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). These lines should be connected to a positive supply, via a pullup resistor and remain HIGH even when the bus is idle.

For every device on the bus is assigned a unique address and it acts as a master or a slave, depending on whether it generates or receives the SCL. When LP55281 is connected in parallel with other I²C compatible devices, the LP55281 supply voltages V_DD1, V_DD2 and V_DDIO must be active. Supplies are required to make sure that the LP55281 does not disturb the SDA and SCL lines.

7.5.2.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL. Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line during the high states of the SCL and in the middle of the transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 20. Data Validity

Each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following sections provide further details of this process.

Figure 21. Acknowledge Signal

The Master device on the bus always generates the start and stop conditions (control codes). After a start condition is generated, the bus is considered busy and it retains this status until a certain time after a stop condition is generated. A high-to-low transition of the data line (SDA), while the clock (SCL) is high, indicates a Start Condition. A low-to-high transition of the SDA line, while the SCL is high, indicates a stop condition.

Figure 22. Start And Stop Conditions

In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction. This allows another device to be accessed or a register read cycle.

7.5.2.3 Acknowledge Cycle

The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

7.5.2.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to theacknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

7.5.2.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP55281 operates as a slave device with 7-bit address. LP55281 I²C address is pin selectable from two different choices. The LP55281 address is 4Ch (SI/A0 = 0) or 4Dh (SI/A0 = 1) as selected with SI/A0 pin. If eighth bit is used for programming, the 8^th bit is 1 for read and 0 for write.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address.

The slave address is the first seven bits after a start condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address (the eighth bit).

When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1 for read, 0 for write), the device acts as a transmitter or a receiver.

Figure 23. I²C Device Address

7.5.2.6 Control Register Write Cycle

• Master device generates start condition
• Master device sends slave address (7 bits) and the data direction bit (r/w=0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes, the control register address will be incremented by one after acknowledge signal
• Write cycle ends when the master creates stop condition.

7.5.2.7 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w=0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w=1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

< > Data from master, [ ] data from slave

Figure 24. Register READ Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform.

Figure 25. Register WRITE Format

• w = write (SDA = 0)
• r = read (SDA = 1)
• ack = acknowledge (SDA pulled down by either master or slave)
• rs = repeated start
• id = 7-bit device address