JAJSMR3 December   2021 LP5864

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Time-Multiplexing Matrix
      2. 8.3.2 Analog Dimming (Current Gain Control)
      3. 8.3.3 PWM Dimming
      4. 8.3.4 ON and OFF Control
      5. 8.3.5 Data Refresh Mode
      6. 8.3.6 Full Addressable SRAM
      7. 8.3.7 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5 Data Refresh Mode

The LP5864 supports three data refresh modes: Mode 1, Mode 2, and Mode 3, by configuring 'Data_Ref_Mode' in Dev_initial register.

Mode 1: 8-bit PWM data without VSYNC command. Data is sent out for display instantly after received. With Mode 1, users can refresh the corresponding dots' data only instead of updating the whole SRAM. It is called ‘on demand data refresh’, which can save the total data volume effectively. As shown in Figure 8-7, the red LED dots can be refreshed after sending the corresponding data while the others kept the same with last frame.

Figure 8-7 On Demand Data Refresh - Mode 1

Mode 2: 8-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after receiving the VSYNC command.

Mode 3: 16-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after receiving the VSYNC command.

Frame control is implemented in Mode 2 and Mode 3. Instead of refreshing the output instantly after data is received (Mode 1), the device holds the data and refreshes the whole frame data by a fixed frame rate, fVSYNC. Usually, 24 Hz, 50 Hz, 60 Hz, 120 Hz or even higher frame rate is selected to achieve vivid animation effects. Whole SRAM Data Refresh is shown in Figure 8-8, a new frame is updated after receiving the VSYNC command.

Figure 8-8 Whole SRAM Data Refresh

Comparing with Mode 1, Mode 2 and Mode 3 provide a better synchronization when multiple LP5864 devices used together. A high-level pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame. Figure 8-9 shows the VSYNC connections and Figure 8-10 shows the timing requirements.

Figure 8-9 Multiple Devices Sync
Figure 8-10 VSYNC Timing
Table 8-4 is the summary of the three data refresh modes.
Table 8-4 Data Refresh Mode
MODE TYPEPWM RESOLUTIONPWM OUTPUTEXTERNAL VSYNC
Mode 18 bitsData update instantlyNo
Mode 28 bitsData update by frameYes
Mode 316 bits