JAJSM77 December   2021 LP5868

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Time-Multiplexing Matrix
      2. 8.3.2 Analog Dimming (Current Gain Control)
      3. 8.3.3 PWM Dimming
      4. 8.3.4 ON and OFF Control
      5. 8.3.5 Data Refresh Mode
      6. 8.3.6 Full Addressable SRAM
      7. 8.3.7 Protections and Diagnostics
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

Figure 6-1 LP5868 RKP Package 40-Pin VQFN With Exposed Thermal Pad Top View
Table 6-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
1CS0OCurrent sink 0. If not used, this pin must be left floating.
2CS1OCurrent sink 1. If not used, this pin must be left floating.
3CS2OCurrent sink 2. If not used, this pin must be left floating.
4CS3OCurrent sink 3. If not used, this pin must be left floating.
5CS4OCurrent sink 4. If not used, this pin must be left floating.
6CS5OCurrent sink 5. If not used, this pin must be left floating.
7CS6OCurrent sink 6. If not used, this pin must be left floating.
8CS7OCurrent sink 7. If not used, this pin must be left floating.
9CS8OCurrent sink 8. If not used, this pin must be left floating.
10SW0OHigh-side PMOS switch output for scan line 0. If not used, this pin must be left floating.
11SW1OHigh-side PMOS switch output for scan line 1. If not used, this pin must be left floating.
12SW2OHigh-side PMOS switch output for scan line 2. If not used, this pin must be left floating.
13SW3OHigh-side PMOS switch output for scan line 3. If not used, this pin must be left floating.
14SW4OHigh-side PMOS switch output for scan line 4. If not used, this pin must be left floating.
15SW5OHigh-side PMOS switch output for scan line 5. If not used, this pin must be left floating.
16VLEDPowerPower input for high-side switches
17SW6OHigh-side PMOS switch output for scan line 6. If not used, this pin must be left floating.
18SW7OHigh-side PMOS switch output for scan line 7. If not used, this pin must be left floating.
19NC–No internal connection
20NC–No internal connection
21NC–No internal connection
22CS9OCurrent sink 9. If not used, this pin must be left floating.
23CS10OCurrent sink 10. If not used, this pin must be left floating.
24CS11OCurrent sink 11. If not used, this pin must be left floating.
25CS12OCurrent sink 12. If not used, this pin must be left floating.
26CS13OCurrent sink 13. If not used, this pin must be left floating.
27CS14OCurrent sink 14. If not used, this pin must be left floating.
28CS15OCurrent sink 15. If not used, this pin must be left floating.
29CS16OCurrent sink 16. If not used, this pin must be left floating.
30CS17OCurrent sink 17. If not used, this pin must be left floating.
31AGNDGroundAnalog ground. Must be connected to exposed thermal pad and common ground plane.
32VCAPOInternal LDO output. A 1-μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
33IFSIInterface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
34VSYNCIExternal synchronize signal for display mode 2 and mode 3
35SCL_SCLKII2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
36SDA_MOSII/OI2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
37ADDR0_MISOI/OI2C address select 0 or SPI leader input follower output.
38ADDR1_SSII2C address select 1 or SPI follower select.
39VIO_ENPower,IPower supply for digital circuits and chip enable. A 1-nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
40VCCPowerPower supply for device. A 1-μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
Exposed Thermal PadGNDGroundMust be connected to AGND and common ground plane.