JAJSP11A August   2022  – December 2022 LP5891-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Independent and Stackable Mode
        1. 8.3.1.1 Independent Mode
        2. 8.3.1.2 Stackable Mode
      2. 8.3.2 Current Setting
        1. 8.3.2.1 Brightness Control (BC) Function
        2. 8.3.2.2 Color Brightness Control (CC) Function
        3. 8.3.2.3 Choosing BC/CC for a Different Application
      3. 8.3.3 Frequency Multiplier
      4. 8.3.4 Line Transitioning Sequence
      5. 8.3.5 Protections and Diagnostics
        1. 8.3.5.1 Thermal Shutdown Protection
        2. 8.3.5.2 IREF Resistor Short Protection
        3. 8.3.5.3 LED Open Load Detection and Removal
          1. 8.3.5.3.1 LED Open Detection
          2. 8.3.5.3.2 Read LED Open Information
          3. 8.3.5.3.3 LED Open Caterpillar Removal
        4. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 8.3.5.4.1 LED Short/Weak Short Detection
          2. 8.3.5.4.2 Read LED Short Information
          3. 8.3.5.4.3 LSD Caterpillar Removal
    4. 8.4 Device Functional Modes
    5. 8.5 Continuous Clock Series Interface
      1. 8.5.1 Data Validity
      2. 8.5.2 CCSI Frame Format
      3. 8.5.3 Write Command
        1. 8.5.3.1 Chip Index Write Command
        2. 8.5.3.2 VSYNC Write Command
        3. 8.5.3.3 MPSM Write Command
        4. 8.5.3.4 Standby Clear and Enable Command
        5. 8.5.3.5 Soft_Reset Command
        6. 8.5.3.6 Data Write Command
      4. 8.5.4 Read Command
    6. 8.6 PWM Grayscale Control
      1. 8.6.1 Grayscale Data Storage and Display
        1. 8.6.1.1 Memory Structure Overview
        2. 8.6.1.2 Details of Memory Bank
        3. 8.6.1.3 Write a Frame Data into Memory Bank
      2. 8.6.2 PWM Control for Display
    7. 8.7 Register Maps
      1. 8.7.1  FC0
      2. 8.7.2  FC1
      3. 8.7.3  FC2
      4. 8.7.4  FC3
      5. 8.7.5  FC4
      6. 8.7.6  FC14
      7. 8.7.7  FC15
      8. 8.7.8  FC16
      9. 8.7.9  FC17
      10. 8.7.10 FC18
      11. 8.7.11 FC19
      12. 8.7.12 FC20
      13. 8.7.13 FC21
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 System Structure
        2. 9.2.1.2 SCLK Frequency
        3. 9.2.1.3 Internal GCLK Frequency
        4. 9.2.1.4 Line Switch Time
        5. 9.2.1.5 Blank Time Removal
        6. 9.2.1.6 BC and CC
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Chip Index Command
        2. 9.2.2.2 FC Registers Settings
        3. 9.2.2.3 Grayscale Data Write
        4. 9.2.2.4 VSYNC Command
        5. 9.2.2.5 LED Open, Short Read
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RRF|76
サーマルパッド・メカニカル・データ
発注情報

8.7.2 FC1

FC1 is shown in Figure 8-30 and described in Table 8-8.

Figure 8-30 FC1 Register
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED BLK_ADJ LINE_SWT LG_ENH_B LG_ENH_G
R-0b R/W-000000b R/W-0111b R/W-0000b
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LG_ENH_G LG_ENH_R LG_STEP_B LG_STEP_G
R/W-0000b R/W-0000b R/W-01001b R/W-01001b
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LG_STEP_G LG_STEP_R SEG_LENGTH
R/W-01001b R/W-0'000'000'000b
Table 8-8 FC1 Register Field Descriptions
Bit Field Type Reset Description
9-0 SEG_LENGTH R/W 0'000'000'000b Set the GCLK number in each segment
127d: 128 GCLK
...
1023d: 1024 GCLK
others: 128 GCLK
14-10 LG_STEP_R R/W 01001b Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
19-15 LG_STEP_G R/W 01001b Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
24-20 LG_STEP_B R/W 01001b Adjust the smooth of the brightness in low grayscale
00000b: level 1
...
01111b: level 16
...
11111b: level 32
28-25 LG_ENH_R R/W 0000b Adjust low grayscale enhancement of red channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
32-29 LG_ENH_G R/W 0000b Adjust low grayscale enhancement of green channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
36-33 LG_ENH_B R/W 0000b Adjust low grayscale enhancement of blue channels
0000b: level 0
...
0111b: level 7
...
1111b: level 15
40-37 LINE_SWT R/W 0111b Set the scan line switch time.
0000b: 45 GCLK
0001b: 2x30 GCLK
...
0111b: 8x30 GCLK
...
1111b: 16x30 GCLK
46-41 BLK_ADJ R/W 000000b Set the black field adjustment
000000b: 0 GCLK
...
011111b: 31 GCLK
...
111111b: 63 GCLK
47 RESERVED R 0b Reserved bit.