JAJSEF4P April   2012  – January 2024 LP5907

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Output and Input Capacitors
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Low Output Noise
      3. 6.3.3 Output Automatic Discharge
      4. 6.3.4 Remote Output Capacitor Placement
      5. 6.3.5 Thermal Overload Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Enable (EN)
      2. 6.4.2 Minimum Operating Input Voltage (VIN)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 Power Dissipation and Device Operation
        3. 7.2.2.3 External Capacitors
        4. 7.2.2.4 Input Capacitor
        5. 7.2.2.5 Output Capacitor
        6. 7.2.2.6 Capacitor Characteristics
        7. 7.2.2.7 Remote Capacitor Operation
        8. 7.2.2.8 No-Load Stability
        9. 7.2.2.9 Enable Control
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 X2SON Mounting
        2. 7.4.1.2 DSBGA Mounting
        3. 7.4.1.3 DSBGA Light Sensitivity
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Custom Design With WEBENCH® Tools
      2. 8.1.2 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-F8D1E763-5DFF-41C7-9B07-583E3BAD8BFC-low.gifFigure 4-1 YKE, YKG, YKM, and YCR Packages,4-Pin DSBGA
Table 4-1 Pin Functions: DSBGA
PINTYPEDESCRIPTION
DSBGANAME
A1INIInput voltage supply. Connect a 1µF capacitor at this input.
A2OUTORegulated output voltage. Connect a minimum 1µF low-ESR capacitor to this pin. Connect this output to the load circuit. An internal 230Ω (typical) pulldown resistor prevents a charge remaining on VOUT when the regulator is in the shutdown mode (VEN low).
B1ENIEnable input. A low voltage (< VIL) on this pin turns the regulator off and discharges the output pin to GND through an internal 230Ω pulldown resistor. A high voltage (> VIH) on this pin enables the regulator output. This pin has an internal 1MΩ pulldown resistor to hold the regulator off by default.
B2GND—Common ground
GUID-53DF763F-BA35-464A-AA4C-CD3F60173FD8-low.gifFigure 4-2 DQN Package,4-Pin X2SON
(Bottom View)
GUID-DD7B6398-8F6C-4A00-B53A-45671D4BFAE7-low.gifFigure 4-3 DBV Package,5-Pin SOT-23
(Top View)
Table 4-2 Pin Functions: X2SON, SOT-23
PINTYPEDESCRIPTION
NAMEX2SONSOT-23
EN 3 3 I Enable input. A low voltage (< VIL) on this pin turns the regulator off and discharges the output pin to GND through an internal 230Ω pulldown resistor. A high voltage (> VIH) on this pin enables the regulator output. This pin has an internal 1MΩ pulldown resistor to hold the regulator off by default.
GND 2 2 — Common ground.
IN41IInput voltage supply. Connect a 1µF capacitor at this input.
N/C — 4 — No internal electrical connection.
OUT15ORegulated output voltage. Connect a minimum 1µF low-ESR capacitor to this pin. Connect this output to the load circuit. An internal 230Ω (typical) pulldown resistor prevents a charge remaining on VOUT when the regulator is in shutdown mode (VEN low).
Thermal Pad5——Thermal pad for the X2SON package, connect to GND or leave floating. Do not connect to any potential other than GND.