SNVSAA8C December   2015  – September 2016 LP5912-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Voltage Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Output and Input Capacitors
  8. 8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Enable (EN)
      2. 9.3.2 Output Automatic Discharge (RAD)
      3. 9.3.3 Reverse Current Protection (IRO)
      4. 9.3.4 Internal Current Limit (ISC)
      5. 9.3.5 Thermal Overload Protection (TSD)
      6. 9.3.6 Power-Good Output (PG)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Enable (EN)
      2. 9.4.2 Minimum Operating Input Voltage (VIN)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 External Capacitors
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
        4. 10.2.2.4 Capacitor Characteristics
        5. 10.2.2.5 Remote Capacitor Operation
        6. 10.2.2.6 Power Dissipation
        7. 10.2.2.7 Estimating Junction Temperature
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

The dynamic performance of the LP5912-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5912-Q1.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5912-Q1, and as close to the package as is practical. The ground connections for CIN and COUT must be back to the LP5912-Q1 ground pin using as wide and as short of a copper trace as is practical.

Connections using long trace lengths, narrow trace widths, or connections through vias must be avoided. Such connections add parasitic inductances and resistance that result in inferior performance especially during transient conditions.

12.2 Layout Example

LP5912-Q1 layout_snvsa77.gif Figure 57. LP5912-Q1 Typical Layout