11.1 Layout Guidelines

Figure 27 is a layout recommendation for the LP8551. The figure is used for demonstrating the principle of good layout. This layout can be adapted to the actual application layout if/where possible.

It is important that all boost components are close to the chip and the high current traces should be wide enough. By placing the boost component on one side of the chip it is easy to keep the ground plane intact below the high current paths. This way other chip pins can be routed more easily without splitting the ground plane. If the chip is placed in the center of the boost components, the I²C lines, LED lines, etc. cut the ground plane below the high current paths, and it makes the layout design more difficult.

V_IN and V_LDO need to be as noise-free as possible. Place the bypass capacitors near the corresponding pins and ground them to as noise-free ground as possible.

Here are some main points to help the PCB layout work:

1. Current loops need to be minimized:
   1. For low frequency the minimal current loop can be achieved by placing the boost components as close to the SW and SW_GND pins as possible. Input and output capacitor grounds need to be close to each other.
   2. Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents try to find route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the “positive” current route in the ground plane, if the ground plane is intact under the route. Traces from inner pads of the LP8551 need to be routed from below the part in the second layer so that traces do not split the ground plane under the boost traces or components.
2. GND plane needs to be intact under the high current boost traces to provide shortest possible return path and smallest possible current loops for high frequencies.
3. Current loops when the boost switch is conducting and not conducting needs to be on the same direction in optimal case.
4. Inductor placement should be so that the current flows in the same direction as in the current loops. Rotating inductor 180 degrees changes current direction.
5. Use separate “noisy” and “silent” grounds. Noisy ground is used for boost converter return current and silent ground for more sensitive signals, like VIN and V_LDO bypass capacitor grounding.
6. Boost output voltage to LEDs need to be taken out “after” the output capacitors, not straight from the diode cathode.
7. Small (such as 39 pF) bypass capacitor should be placed close to the FB pin.
8. R_ISET resistor should be grounded to silent gound, since possible ground ripple will show at the LED current.
9. VIN line should be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. Separate 100-nF bypass capacitor is used for VIN line and it is grounded to noise-free ground.
10. Input and output capacitors need strong grounding (wide traces, vias to GND plane).
11. If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.
12. Output capacitors DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable on some loads and this increases EMI. DC bias characteristics need to be obtained from the component manufacturer; it is not taken into account on component tolerance. 50-V 1210-size X5R/X7R capacitors are recommended.

Figure 26. LP8551 Application Schematic

11.2 Layout Example

Figure 27. LP8551 Layout