SNVSA15B December   2013  – December 2015 LP8557

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Function and Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Boost Converter Electrical Characteristics
    7. 7.7  LED Driver Electrical Characteristics (LED1 To LED6 Pins)
    8. 7.8  PWM Interface Characteristics (PWM Pin)
    9. 7.9  Logic Interface Characteristics (PWM, FSET/SDA, ISET/SCL Pins)
    10. 7.10 I2C Serial Bus Timing Parameters (SDA, SCL)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Boost Converter Overview
        1. 8.3.1.1 Operation
        2. 8.3.1.2 Adaptive Boost Output Voltage Control
      2. 8.3.2 Brightness Control
        1. 8.3.2.1 PWM Input Duty Measurement
        2. 8.3.2.2 BRTMODE = 00b
        3. 8.3.2.3 BRTMODE = 01b
        4. 8.3.2.4 BRTMODE = 10b
        5. 8.3.2.5 BRTMODE = 11b
        6. 8.3.2.6 Hybrid PWM & I Dimming Control
        7. 8.3.2.7 Phase Shift PWM Scheme
      3. 8.3.3 Slope and Advanced Slope
      4. 8.3.4 LED String Count Auto Detection
      5. 8.3.5 EMI Reduction Schemes
      6. 8.3.6 Fault Detection
        1. 8.3.6.1 LED Short Detection
        2. 8.3.6.2 LED OPEN* Detection
        3. 8.3.6.3 Undervoltage Detection
        4. 8.3.6.4 Thermal Shutdown
        5. 8.3.6.5 Boost Overcurrent Protection
        6. 8.3.6.6 Boost Overvoltage Protection
        7. 8.3.6.7 Boost Undervoltage Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Bus Interface
        1. 8.5.1.1 Interface Bus Overview
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Data Transactions
        4. 8.5.1.4 Acknowledge Cycle
        5. 8.5.1.5 Acknowledge After Every Byte Rule
        6. 8.5.1.6 Control Register Write Cycle
        7. 8.5.1.7 Control Register Read Cycle
        8. 8.5.1.8 Register Read and Write Detail
    6. 8.6 Register Maps
      1. 8.6.1 Register Bit Descriptions
        1. 8.6.1.1  COMMAND
        2. 8.6.1.2  STATUS
        3. 8.6.1.3  BRTLO
        4. 8.6.1.4  BRTHI
        5. 8.6.1.5  CONFIG
        6. 8.6.1.6  CURRENT
        7. 8.6.1.7  PGEN
        8. 8.6.1.8  BOOST
        9. 8.6.1.9  LEDEN
        10. 8.6.1.10 STEP
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Designing With LP8557
        1. 9.1.1.1 Setting Boost Switching and PWM Dimming Frequencies
        2. 9.1.1.2 Setting Boost Compensation
        3. 9.1.1.3 Setting Full-Scale Led Current
      2. 9.1.2 Designing With LP8557I
        1. 9.1.2.1 Setting Boost Switching Frequency
        2. 9.1.2.2 Setting Boost Compensation
        3. 9.1.2.3 Setting PWM Dimming Frequency
        4. 9.1.2.4 Setting Full-Scale LED Current
    2. 9.2 Typical Applications
      1. 9.2.1 LP8557 PWM-Only Option
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Boost Output Capacitor Selection
          2. 9.2.1.2.2 Schottky Diode Selection
          3. 9.2.1.2.3 Inductor Selection
          4. 9.2.1.2.4 Boost Input andVDD Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 LP8557I PWM and I2C Device Option
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Boost Output Capacitor Placement
      2. 11.1.2 Schottky Diode Placement
      3. 11.1.3 Inductor Placement
      4. 11.1.4 Boost Input and VDD Capacitor Placement
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

Figure 50 shows an example layout which applies the required proper layout guidelines to be used as a guide for laying out the LP8557 circuit.

Table 12. Application Circuit Component List

COMPONENT MANUFACTURER VALUE PART NUMBER SIZE (mm) CURRENT/VOLTAGE RATING, RESISTANCE, TEMPERATURE
L Cyntec 10 µH PIME051E 5.4 × 5.2 × 1.5 2 A, 0.153 Ω
COUT Murata 4.7 µF (×2) GRM188R6YA475KE15D 0603
(1.6 × 0.8 × 0.8)		 35 V, X5R
CIN TDK 10 µF C1608X5R1A106M080AC 0603
(1.6 × 0.8 × 0.8)		 10 V, X5R
Diode Rohm Semiconductor Schottky RB160M-40 SOD-123
(3.5 × 1.6 × 0.8)		 VR = 40 V, VF = 0.5 V

The following guidelines apply to both LP8557 and LP8557I.

The LP8557 inductive boost converter sees a high switched voltage at the SW pin, and a step current through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = C × dV/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW and FB pins due to parasitic inductance in the step current conducting path (V = L × di/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise. Figure 48 highlights these two noise-generating components.

LP8557 LP85571 inductive_boost_converter.gif Figure 48. LP8557 Inductive Boost Converter Showing Pulsed Voltage at SW (High dv/dt) And Current Through the Schottky Diode and COUT (High di/dt)

The following list details the main (layout sensitive) areas of the LP8557’s inductive boost converter in order of decreasing importance:

  1. Output Capacitor
    • COUT+ to Schottky diode cathode connection
    • COUT– to GND bump of the LP8557 connection
  2. Schottky Diode
    • Schottky diode anode to SW connection
    • Schottky diode cathode to COUT+ connection
  3. Inductor
    • SW Node PCB capacitance to other traces
  4. Input Capacitor
    • CIN+ to VDD bump connection
    • CIN– to GND connection

11.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path, it detects a high-current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series path from the diodes cathode, through COUT, and back into the LP8557 GND pin contributes to voltage spikes (VSPIKE = LP_ × dI/dt) at SW and OUT. These spikes can potentially over-voltage the SW and FB pins, or feed through to GND. To avoid this, COUT+ must be connected as close to the cathode of the Schottky diode as possible, and COUT− must be connected as close to the LP8557 GND pins as possible. The best placement for COUT is on the same layer as the LP8557 to avoid any vias that can add excessive series inductance.

11.1.2 Schottky Diode Placement

In the LP8557’s boost circuit the Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off, and the diode turns on. Any inductance in series with the diode can cause a voltage spike (VSPIKE = LP_ × dI/dt) at SW and OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor, into GND. Connecting the anode of the diode as close to the SW pin as possible, and connecting the cathode of the diode as close to COUT+ as possible, reduces the inductance (LP_) and minimize these voltage spikes.

11.1.3 Inductor Placement

The node where the inductor connects to the LP8557 SW bump has 2 challenges. First, a large switched voltage (0 to (VOUT + VF_SCHOTTKY)) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW bump. Any resistance in this path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range.

To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high-impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not directly adjacent or beneath. This is especially true for traces such as ISET/SCL, FSET/SDA, and PWM. A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.

Lastly, limit the trace resistance of the VBATT-to-inductor connection and from the inductor-to-SW connection, by use of short, wide traces.

11.1.4 Boost Input and VDD Capacitor Placement

The LP8557 input capacitor filters the inductor current ripple and the internal MOSFET driver currents. The inductor current ripple can add input voltage ripple due to any series resistance in the input power path. The MOSFET driver currents can add voltage spikes on the input due to the inductance in series with the VIN/VDD and the input capacitor. Close placement of the input capacitor to the VDD pin and to the GND pin is critical because any series inductance between VIN/VDD and CIN+ or CIN– and GND can create voltage spikes that could appear on the VIN/VDD supply line and GND.

Close placement of the input capacitor at the input side of the inductor is also critical. The source impedance (inductance and resistance) from the input supply, along with the input capacitor of the LP8557, forms a series RLC circuit. If the output resistance from the source (RS, Figure 49) is low enough, the circuit is underdamped and has a resonant frequency (typically the case). Depending on the size of LS, the resonant frequency could occur below, close to, or above the LP8557's switching frequency. This can cause the supply current ripple to be:

  1. Approximately equal to the inductor current ripple when the resonant frequency occurs well above the LP8557 switching frequency.
  2. Greater than the inductor current ripple when the resonant frequency occurs near the switching frequency.
  3. Less than the inductor current ripple when the resonant frequency occurs well below the switching frequency. Figure 49 shows the series RLC circuit formed from the output impedance of the supply and the input capacitor.

The circuit is redrawn for the AC case where the VIN supply is replaced with a short to GND and the LP8557 + Inductor is replaced with a current source (ΔIL). Equation 1 is the criteria for an under-damped response. Equation 2 is the resonant frequency. Equation 3 is the approximated supply current ripple as a function of LS, RS, and CIN.

As an example, consider a 3.8-V supply with 0.1-Ω of series resistance connected to CIN (10 µF) through 50 nH of connecting traces. This results in an under-damped input-filter circuit with a resonant frequency of 225 kHz. Because both the 1-MHz and 500-kHz switching frequency options lie above the resonant frequency of the input filter, the supply current ripple is probably smaller than the inductor current ripple. In this case, using Equation 3, the supply current ripple can be approximated as 0.2 times the inductor current ripple (using a 500-kHz switching frequency) and 0.051 times the inductor current ripple using a 1-MHz switching frequency.

LP8557 LP85571 inputRLC_network.gif Figure 49. Input RLC Network

11.2 Layout Example

LP8557 LP85571 layout_example.gif Figure 50. LP8557 and LP8557I Layout Example

Low-pass filter near VDD input pin is recommended for noisy power condition to prevent unstable LED current. 10 Ω plus approximately 2.2 µF to 10 µF can be used as low-pass filter components.