SNVSA72 February   2015 LP8728D-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Information
        1. 7.3.1.1 Features
      2. 7.3.2 Thermal Shutdown (TSD)
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Overvoltage Protection (OVP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor
        2. 8.2.2.2 Input and Output Capacitors
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Documentation
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP8728D-Q1 is a quad-output Power Management Unit (PMU), optimized for low-power FPGAs, microprocessors, and DSPs.

8.2 Typical Application

Figure 15 shows an example of a typical application. A microcontroller controls each buck converter with separate enable signals. All four power good signals are connected to a microcontroller with dedicated pullup resistors. If only one master power good signal is required all power good signals can be connected in parallel and pulled up with a single pullup resistor. VOUT3 output voltage can be selected with a DEFSEL input. If VOUT3 output voltage control is not required during operation, output voltage can be selected by connecting DEFSEL pin to VDDIO or to GND.

LP8728_Typ_app_141219.gifFigure 15. LP8728D-Q1 Typical Application Schematic

8.2.1 Design Requirements

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range (VIN) 4.5 V to 5.5 V
Buck converter output current 1 A maximum
Buck converter input capacitance 10 µF, 6.3 V
Buck converter output capacitance 10 µF, 6.3 V
Buck converter inductor 1.5 µH, 1.5 A
AVDD pin bypass capacitor 1 µF, 6.3 V
BYP pin bypass capacitor 1 µF, 6.3 V

8.2.2 Detailed Design Procedure

8.2.2.1 Inductor

The four converters operate with 1.5-µH inductors. The inductor has to be selected based on the DC resistance and saturation current. The DC resistance of the inductor directly effects the efficiency of the converter. Therefore, an inductor with the lowest possible DC resistance should be selected for good efficiency. The inductor should have a saturation current rating equal or higher than the high-side switch current limit (1500 mA). To minimize radiated noise shielded inductor should be used. The inductor should be placed as close to the LP8728D-Q1 as possible, and the trace from the inductor to the buck converter switch pin needs to be wide enough to withstand the high switching currents.

8.2.2.2 Input and Output Capacitors

Because buck converters have a discontinuous input current, a low equivalent series resistance (ESR) input capacitor is required for the best input-voltage filtering and to minimize interference with other circuits caused by high input voltage spikes. Each DC-DC converter requires a 10-µF ceramic input capacitor on its input pin VIN_Bx. The input capacitor capacitance can be increased without any limit for better input voltage filtering. Voltage rating of the capacitors should be at least 10V. A small 100-nF capacitor can be used in parallel to minimize high-frequency interferences. Input capacitors should be placed as close to the VIN_Bx pins as possible. Routing from input capacitor to VIN_Bx pins should be done on top layer without using any vias.

An output capacitor with a typical value of 10 µF is recommended for each converter. Ceramic capacitors with low ESR value have lowest output voltage ripple and are recommended.

Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied DC voltage (DC bias effect). The capacitance value can fall below half of the nominal capacitance. This needs to be taken into consideration and, if necessary, use a capacitor with higher value or higher voltage rating.

Table 1. Recommended External Components

COMPONENT DESCRIPTION VALUE TYPE EXAMPLE
CIN_B1,2,3,4 Buck regulator input capacitor 10 µF Ceramic, 10 V, X7R MuRata, GRM21BR71A106KE51L
COUT_B1,2,3,4 Buck regulator output capacitor 10 µF Ceramic, 10 V, X7R MuRata, GRM21BR71A106KE51L
CAVDD AVDD pin input capacitor 1 µF Ceramic, 10 V, X7R MuRata, GRM188R71A105KA61D
CBYP Internal LDO bypass capacitor 1 µF Ceramic, 10 V, X7R MuRata, GRM188R71A105KA61D
LSW1,2,3 4 Buck regulator inductor 1.5 µH ISAT >1.5 A, DCR < 100 mΩ TOKO MDT2520-CN1R5M

8.2.3 Application Performance Plots

Unless otherwise noted, VIN = 5 V, TA = 25°C, inductor type: TOKO MDT2520-CN1R5M, input and output capacitor type: MuRata GRM21BR71A106KE51L.
C014_SNVS972.png
Figure 16. Short-Circuit Waveforms
C016_SNVS972.png
IOUT from 0 mA to 1A, tRISE = tFALL = 1 µs
Figure 18. Load Transient Response
C013_SNVS972.png
Figure 20. Switch Turn-on Phase Shifting
C015_SNVS972.png
Figure 17. Start-up Delay
C017_SNVS972.png
VIN from 4.5 V To 5.5 V, tRISE = tFALL = 10 µs
Figure 19. Line Transient Response