Table 3. Supply Specification

8.3.1 Linear Low Dropout Regulators (LDOs)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control register. The output voltages of both LDOs are register programmable. The default output voltages are factory programmed during Final Test, which can be tailored to the specific needs of the system designer.

Figure 11. LDO Functional Block Diagram

8.3.2 No-Load Stability

The LDOs remain stable and in regulation with no external load. This is an important consideration in some circuits, for example, CMOS RAM keep-alive applications.

8.3.3 LDO1 and LDO2 Control Registers

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is programmable in steps of 100 mV from 1 V to 3.5 V by programming bits D4 to D0 in the LDO Control registers. Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the register is logic 1 by default. The output voltage can be altered while the LDO is enabled.

8.3.4 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters

8.3.4.2 Circuit Operation

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BUCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of

Equation 1.

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of

Equation 2.

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load.

8.3.4.12 Power-Up Sequencing Using the EN_T Function

EN_T assertion causes the LP8731-Q1 to emerge from Standby mode to Full Operation mode at a preset timing sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are internally pulled down by a 500-kΩ resistor, which causes the part to stay OFF until enabled. If the user wishes to use the preset timing sequence to power on the regulators, transition the EN_T pin from LOW to HIGH. Otherwise, simply tie the enables of each specific regulator HIGH to turn on automatically.

EN_T is edge triggered with rising edge signaling the device to power on. The EN_T input is deglitched, and the default is set at 1 ms. As shown in Figure 12 and Figure 13, a rising EN_T edge starts a power-on sequence, while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the regulators has no effect on the device.

The regulators can also be programmed through I²C to turn on and off. By default, I²C enables for the regulators on ON.

The regulators are on following the pattern: Regulators on = (I²C enable) AND (External pin enable OR EN_T high).

NOTE

The EN_T power-up sequencing may also be employed immediately after V_IN is applied to the device. However, V_IN must be stable for approximately 8 ms minimum before EN_T be asserted high to ensure internal bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first time device power on for power-sequencing function to operate properly.

Figure 12. Enable Logic Diagram

Figure 13. LP8731-Q1 Default Power-Up Sequence

Table 4. Power-On Timing Specification

		MIN	NOM	MAX	UNIT
t1	Programmable delay from EN_T assertion to VCC_Buck1 on		1.5		ms
t2	Programmable delay from EN_T assertion to VCC_Buck2 on		2		ms
t3	Programmable delay from EN_T assertion to VCC_LDO1 on		3		ms
t4	Programmable delay from EN_T assertion to VCC_LDO2 on		6		ms

Figure 14. LP8731-Q1 Default Power-Off Sequence

		MIN	NOM	MAX	UNIT
t1	Programmable delay from EN_T deassertion to VCC_Buck1 off		1.5		ms
t2	Programmable delay from EN_T deassertion to VCC_Buck2 off		2		ms
t3	Programmable delay from EN_T deassertion to VCC_LDO1 off		3		ms
t4	Programmable delay from EN_T deassertion to VCC_LDO2 off		6		ms

NOTE

The LP8731-Q1 default power-off delay setting is the same as the on sequence.

8.3.5 Flexible Power-On Reset (for example, Power Good with Delay)

The LP8731-Q1 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage levels on bucks 1 and 2. The nPOR is an open-drain logic output which is logic LOW when either of the buck outputs are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and when nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms), 50 µs by default. The system designer can choose the external pull-up resistor (for example, 100 kΩ) for the nPOR pin.

Figure 15. nPOR With Counter Delay

Figure 15 shows the simplest application of the Power-On Reset, where both switcher enables are tied together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for Buck2 does not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the vice-versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay before going HIGH, as explained in Figure 16.

Figure 16. Faults Occurring in Counter Delay after Start-Up

The Figure 16 timing diagram details the power-good with delay with respect to the enable signals EN1, and EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been trimmed as follows:

The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also works for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are HIGH at time t1, then the RDY1 signal rising edge triggers the programmable delay counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is then pulled HIGH after the programmable delay is completed. If EN2 and RDY2 are initiated during this interval, the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

Figure 17. nPOR Mask Window

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted .

Case 1 in Figure 17 shows a case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising edge. nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on the status of both RDY1 and RDY2 lines.

Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never goes HIGH (Buck2 never turns on). Normal operation of nPOR occurs with respect to EN1 and RDY1, and the nPOR signal is held HIGH for the duration of the mask window. nPOR goes LOW after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

Figure 18. Design Implementation Of The Flexible Power-On Reset

An internal power-on reset of the device is used with EN1 and EN2 to produce a reset signal (LOW) to the delay timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer. S = R = 1 never occurs. The mask timers are triggered by EN1 and EN2 which are gated with RDY1 and RDY2 to generate outputs to the final AND gate to generate the nPOR.

8.3.6 Undervoltage Lockout

The LP8731-Q1 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC.

The circuit incorporates a bandgap-based circuit that establishes the reference used to determine the 2.8-VDC trip point for a V_IN OK – Not OK detector. This V_IN OK signal is then used to gate the enable signals to the four regulators of the LP8731-Q1. When VINLDO12 is greater than 2.8 VDC, the four enables control the four regulators, when VINLDO12 is less than 2.8 VDC, the four regulators are disabled by the V_IN detector being in the “Not OK” state. The circuit has built-in hysteresis to prevent chattering from occurring.

8.4.1 Shutdown Mode

During shutdown the PFET switch, reference, control, and bias circuitry of the converters are turned off. The NFET switch is turned on during shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended that the converter be disabled during the system power up and undervoltage conditions when the supply is less than 2.8 V.

8.5.1 I²C-Compatible Serial Interface

8.5.1.2 I²C Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), that is, the state of the data line can only be changed when CLK is LOW.

Figure 19. I²C Signals: Data Validity

8.5.1.3 I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while the SCL is HIGH. The I²C master always generates START and STOP bits. The I²C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I²C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise.

Figure 20. Start And Stop Conditions

8.5.1.4 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been addressed must generate an acknowledgment (“ACK”) after each byte has been received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W).

NOTE

According to industry I²C standards for 7-bit addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register.

The LP8731-Q1 has factory-programmed I²C addresses. The device has a chip address of 59'h.

Figure 21. I²C Chip Address (see NOTE above)

w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = LP8731-Q1 chip address: 0x59

Figure 22. I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform.

Figure 23. I²C Read Cycle

8.6.1 Interrupt Status Register (ISRA) 0x02

This register informs the system engineer of the temperature status of the chip.

8.6.2 System Control 1 Register (SCR1) 0x07

This register allows the user to select the preset delay sequence for power-on timing and to select between an internal and external clock for the bucks.

8.6.3 EN_DLY Preset Delay Sequence after EN_T Assertion

8.6.4 Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10

This register controls the enables for the Bucks and LDOs.

8.6.5 Buck and LDO Status Register (BKLDOSR) – 0x11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

8.6.6 BUCK Voltage Change Control Register 1 (VCCR) – 0x20

This register selects and controls the output target voltages for the buck regulators.

8.6.7 BUCK1 Target Voltage 1 Register (B1TV1) – 0x23

This register allows the user to program the output target voltage of Buck1 (target voltage 1).

8.6.8 BUCK1 Target Voltage 2 Register (B1TV2) - 0x24

This register allows the user to program the output target voltage of Buck1 (target voltage 2).

8.6.9 BUCK1 Ramp Control Register (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck1.

8.6.10 BUCK2 Target 1 Register (B2TV1) - 0x29

This register allows the user to program the output target voltage of Buck2 (target voltage 1).

8.6.11 BUCK2 Target 2 Register (B2TV2) - 0x2A

This register allows the user to program the output target voltage of Buck2 (target voltage 2).

8.6.12 BUCK2 Ramp Control Register (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck2.

8.6.13 BUCK Function Register (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the frequency ramps up and down, centered at 2 MHz.

Figure 24. Spread Spectrum Frequency Modulation

8.6.14 Spread Spectrum Function

Periodic switching in the buck regulator is inherently a noisier function block compared to an LDO. It can be challenging in some critical applications to comply with stringent regulatory standards or simply to minimize interference to sensitive circuits in space limited portable systems. The regulator’s switching frequency and harmonics can cause "noise" in the signal spectrum. The magnitude of this noise is measured by its power spectral density. The power spectral density of the switching frequency, FC, is one parameter that system designers want to be as low as practical to reduce interference to the environment and subsystems within their products. The LP8731-Q1 has a user-selectable function on the device, allowing a noise-reduction technique known as spread spectrum to be employed to ease customer’s design and production issues.

The principle behind spread spectrum is to modulate the switching frequency slightly and slowly, and spread the signal frequency over a broader bandwidth. Thus, its power spectral density becomes attenuated, used as a spread spectrum clock via two I₂C control register bits bk_ssen, and slomod. With this feature enabled, the intense energy of the clock frequency can be spread across a small band of frequencies in the neighborhood of the center frequency. The results in a reduction of the peak energy!

The LP8731-Q1 spread spectrum clock uses a triangular modulation profile with equal rise and fall slopes. The modulation has the following characteristics:

• The center frequency: FC = 2 MHz, and
• The modulating frequency, ƒM = 6.8 kHz or 12 kHz.
• Peak frequency deviation: Δ_ƒ = ±100 kHz (or ±5%)
• Modulation index β = Δ_ƒ/ƒM = 14.7 or 8.3

This register also allows dynamic scaling of the nPOR Delay Timing. The LP8731-Q1 is equipped with an internal Power-On Reset (POR) circuit which monitors the output voltage levels on the buck regulators, allowing the user to more actively monitor the power status of the device. The undervoltage lockout feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging the power source (for example, the battery), but can be disabled if the user wishes.

The UVLO feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging the power source (for example, the battery), but can be disabled if the user wishes.

8.6.15 LDO1 Control Register (LDO1VCR) – 0x39

This register allows the user to program the output target voltage of LDO1.

8.6.16 LDO2 Control Register (LDO2VCR) – 0x3A

This register allows the user to program the output target voltage of LDO2.