SNVSA28 December   2014 LP8731-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions (Bucks)
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 And LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power-On Reset Threshold/Function (POR)
    10. 7.10 I2C-Compatible Interface Timing
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Features Description
      1. 8.3.1 Linear Low Dropout Regulators (LDOs)
      2. 8.3.2 No-Load Stability
      3. 8.3.3 LDO1 and LDO2 Control Registers
      4. 8.3.4 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.4.1  Functional Description
        2. 8.3.4.2  Circuit Operation
        3. 8.3.4.3  PWM Operation
        4. 8.3.4.4  Internal Synchronous Rectification
        5. 8.3.4.5  Current Limiting
        6. 8.3.4.6  SW1, SW2 Operation
        7. 8.3.4.7  SW1, SW2 Control Registers
        8. 8.3.4.8  Shutdown Mode
        9. 8.3.4.9  Soft Start
        10. 8.3.4.10 Low Dropout Operation
        11. 8.3.4.11 Flexible Power Sequencing of Multiple Power Supplies
        12. 8.3.4.12 Power-Up Sequencing Using the EN_T Function
      5. 8.3.5 Flexible Power-On Reset (for example, Power Good with Delay)
      6. 8.3.6 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
    6. 8.6 LP8731-Q1 Register Maps
      1. 8.6.1  Interrupt Status Register (ISRA) 0x02
      2. 8.6.2  System Control 1 Register (SCR1) 0x07
      3. 8.6.3  EN_DLY Preset Delay Sequence after EN_T Assertion
      4. 8.6.4  Buck and LDO Output Voltage Enable Register (BKLDOEN) - 0x10
      5. 8.6.5  Buck and LDO Status Register (BKLDOSR) - 0x11
      6. 8.6.6  BUCK Voltage Change Control Register 1 (VCCR) - 0x20
      7. 8.6.7  BUCK1 Target Voltage 1 Register (B1TV1) - 0x23
      8. 8.6.8  BUCK1 Target Voltage 2 Register (B1TV2) - 0x24
      9. 8.6.9  BUCK1 Ramp Control Register (B1RC) - 0x25
      10. 8.6.10 BUCK2 Target 1 Register (B2TV1) - 0x29
      11. 8.6.11 BUCK2 Target 2 Register (B2TV2) - 0x2A
      12. 8.6.12 BUCK2 Ramp Control Register (B2RC) - 0x2B
      13. 8.6.13 BUCK Function Register (BFCR) - 0x38
      14. 8.6.14 Spread Spectrum Function
      15. 8.6.15 LDO1 Control Register (LDO1VCR) - 0x39
      16. 8.6.16 LDO2 Control Register (LDO2VCR) - 0x3A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
          1. 9.2.2.1.1 Inductors for SW1 and SW2
            1. 9.2.2.1.1.1 Method 1:
            2. 9.2.2.1.1.2 Method 2:
          2. 9.2.2.1.2 External Capacitors
        2. 9.2.2.2 LDO Capacitor Selection
          1. 9.2.2.2.1 Input Capacitor
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Capacitor Characteristics
          4. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2
          5. 9.2.2.2.5 Output Capacitor Selection for SW1, SW2
          6. 9.2.2.2.6 I2C Pull-up Resistor
          7. 9.2.2.2.7 Operation Without I2C Interface
        3. 9.2.2.3 Junction Temperature
      3. 9.2.3 Application Curves (LDO)
      4. 9.2.4 Application Curves (BUCK)
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Signal Routing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DSBGA (YZR) Package
25 Pins
Top View
30017890.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NUMBER NAME
A1 VINLDO1 I PWR VINLDO1 power in from either DC source or battery to input pin to LDO1.
A2 LDO1 O PWR LDO1 Output
A3 ENLDO2 I D LDO2 enable pin, a logic HIGH enables the LDO2
A4 LDO2 O PWR LDO2 Output
A5 VINLDO2 I PWR VINLDO2 power in from either DC source or battery to input pin to LDO2.
B1 GND_L G G LDO ground
B2 SCL I D I2C Clock
B3 ENLDO1 I D LDO1 enable pin, a logic HIGH enables the LDO1
B4, B5 VINLDO12 I PWR Analog power for internal functions (VREF, BIAS, I2C, Logic)
C1 GND_SW2 G G Buck2 NMOS Power ground
C2 SDA I/O D I2C Data (bidirectional)
C3 nPOR O D nPOR power-on reset pin for both Buck1 and Buck2. Open drain logic output 100K pull-up resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See Flexible Power-On Reset (for example, Power Good with Delay) section for more info.
C4 EN_T I D Enable for preset power-on sequence. (See Flexible Power-On Reset (for example, Power Good with Delay).)
C5 GND_SW1 G G Buck1 NMOS power ground
D1 SW2 O PWR Buck2 switcher output pin
D2 ENSW2 I D Enable pin for Buck2 switcher, a logic HIGH enables Buck2
D3 GND_C G G Non-switching core ground pin
D4 ENSW1 I D Enable pin for Buck1 switcher, a logic HIGH enables Buck1
D5 SW1 O PWR Buck1 switcher output pin
E1 VIN2 I PWR VIN2 power in from either DC source or Battery to Buck2
E2 FB2 I A Buck2 input feedback pin
E3 AVDD I PWR Analog Power for Buck converters
E4 FB1 I A Buck1 input feedback pin
E5 VIN1 I PWR VIN1 power in from either DC source or Battery to Buck1
A: Analog Pin; D: Digital Pin; G: Ground Pin; PWR: Power Pin; I: Input Pin; O: Output Pin; I/O: Input/Output Pin