JAJSF48 March   2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 Multi-Phase DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multiphase Operation, Phase Adding, and Phase-Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multiphase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load-Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Sync Clock Functionality
      3. 8.3.3 Power-Up
      4. 8.3.4 Regulator Control
        1. 8.3.4.1 Enabling and Disabling Regulators
        2. 8.3.4.2 Changing Output Voltage
      5. 8.3.5 Enable and Disable Sequences
      6. 8.3.6 Device Reset Scenarios
      7. 8.3.7 Diagnosis and Protection Features
        1. 8.3.7.1 Power-Good Information (PGOOD Pin)
        2. 8.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 8.3.7.2.1 Output Power Limit
          2. 8.3.7.2.2 Thermal Warning
        3. 8.3.7.3 Protection (Regulator Disable)
          1. 8.3.7.3.1 Short-Circuit and Overload Protection
          2. 8.3.7.3.2 Overvoltage Protection
          3. 8.3.7.3.3 Thermal Shutdown
        4. 8.3.7.4 Fault (Power Down)
          1. 8.3.7.4.1 Undervoltage Lockout
      8. 8.3.8 GPIO Signal Operation
      9. 8.3.9 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto-Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  OTP_REV
        2. 8.6.1.2  BUCK0_CTRL1
        3. 8.6.1.3  BUCK0_CTRL2
        4. 8.6.1.4  BUCK1_CTRL1
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL1
        7. 8.6.1.7  BUCK2_CTRL2
        8. 8.6.1.8  BUCK3_CTRL1
        9. 8.6.1.9  BUCK3_CTRL2
        10. 8.6.1.10 BUCK0_VOUT
        11. 8.6.1.11 BUCK0_FLOOR_VOUT
        12. 8.6.1.12 BUCK1_VOUT
        13. 8.6.1.13 BUCK1_FLOOR_VOUT
        14. 8.6.1.14 BUCK2_VOUT
        15. 8.6.1.15 BUCK2_FLOOR_VOUT
        16. 8.6.1.16 BUCK3_VOUT
        17. 8.6.1.17 BUCK3_FLOOR_VOUT
        18. 8.6.1.18 BUCK0_DELAY
        19. 8.6.1.19 BUCK1_DELAY
        20. 8.6.1.20 BUCK2_DELAY
        21. 8.6.1.21 BUCK3_DELAY
        22. 8.6.1.22 GPIO2_DELAY
        23. 8.6.1.23 GPIO3_DELAY
        24. 8.6.1.24 RESET
        25. 8.6.1.25 CONFIG
        26. 8.6.1.26 INT_TOP1
        27. 8.6.1.27 INT_TOP2
        28. 8.6.1.28 INT_BUCK_0_1
        29. 8.6.1.29 INT_BUCK_2_3
        30. 8.6.1.30 TOP_STAT
        31. 8.6.1.31 BUCK_0_1_STAT
        32. 8.6.1.32 BUCK_2_3_STAT
        33. 8.6.1.33 TOP_MASK1
        34. 8.6.1.34 TOP_MASK2
        35. 8.6.1.35 BUCK_0_1_MASK
        36. 8.6.1.36 BUCK_2_3_MASK
        37. 8.6.1.37 SEL_I_LOAD
        38. 8.6.1.38 I_LOAD_2
        39. 8.6.1.39 I_LOAD_1
        40. 8.6.1.40 PGOOD_CTRL1
        41. 8.6.1.41 PGOOD_CTRL2
        42. 8.6.1.42 PGOOD_FLT
        43. 8.6.1.43 PLL_CTRL
        44. 8.6.1.44 PIN_FUNCTION
        45. 8.6.1.45 GPIO_CONFIG
        46. 8.6.1.46 GPIO_IN
        47. 8.6.1.47 GPIO_OUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Inductor Selection
        2. 9.2.1.2 Input Capacitor Selection
        3. 9.2.1.3 Output Capacitor Selection
        4. 9.2.1.4 Snubber Components
        5. 9.2.1.5 Supply Filtering Components
        6. 9.2.1.6 Current Limit vs. Maximum Output Current
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RNF|26
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ +140°C, CPOL = 22 µF/phase, specified VVANA, VVIN_Bx , VNRST, VVOUT_Bx, and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN Input filtering capacitance Connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT Output filtering capacitance per phase, local 10 22 µF
CPOL Optional point-of-load (POL) capacitance per phase 22 µF
COUT-TOTAL Total output capacitance(3) (local and POL) 4-phase output Output voltage slew-rate ≤ 1.9 mV/µs 2000 µF
3-phase output Output voltage slew-rate ≤ 1.9 mV/µs 1500
2-phase output Output voltage slew-rate ≤ 1.9 mV/µs 1000
1-phase output Output voltage slew-rate ≤ 1.9 mV/µs 500
ESRC ESR of the input and output capacitor 1 MHz ≤ f ≤ 10 MHz 2 10 mΩ
L Inductance of the inductor 0.47 µH
–30% 30%
DCRL Inductor DCR 25 mΩ
BUCK REGULATOR
VVIN_Bx Input voltage range 2.8 3.7 5.5 V
VVOUT_Bx Programmable output voltage range 0.6 3.36 V
Output voltage step size 0.6 V ≤ VVOUT < 0.73 V 10 mV
0.73 V ≤ VVOUT < 1.4 V 5
1.4 V ≤ VVOUT ≤ 3.36 V 20
IOUT Output current(4) 4-phase output VIN ≥ 3 V 16 A
2.8 V ≤ VIN < 3 V 12
3-phase output VIN ≥ 3 V 12
2.8 V ≤ VIN < 3 V 9
2-phase output VIN ≥ 3 V 8
2.8 V ≤ VIN < 3 V 6
1-phase output VIN ≥ 3 V 4
2.8 V ≤ VIN < 3 V 3
Input and output voltage difference
Minimum voltage between VIN_x and VOUT to fulfill the electrical characteristics		 0.5 V
VVOUT_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, and temperature VOUT < 1 V, PWM mode –20 20 mV
VOUT ≥ 1 V, PWM mode –2% 2%
VOUT < 1 V, PFM mode –20 40 mV
VOUT ≥ 1 V, PFM mode –2% 2% + 20 mV
Ripple voltage 4-phase output PWM mode, ESRC < 2 mΩ, L = 0.47 µH 3 mVp-p
PFM mode, L = 0.47 µH 4
3-phase output PWM mode, ESRC < 2 mΩ, L = 0.47 µH 4
PFM mode, L = 0.47 µH 5
2-phase output PWM mode, ESRC < 2 mΩ, L = 0.47 µH 6
PFM mode, L = 0.47 µH 7
1-phase output, PWM mode, ESRC < 2 mΩ, L = 0.47 µH 8
PFM mode, L = 0.47 µH 14
DCLNR DC line regulation IOUT = IOUT(max) 0.1 %/V
DCLDR DC load regulation in PWM mode VOUT = 1 V, 0 A ≤ IOUT ≤ IOUT(max) 0.8%
TLDSR Transient load step response 4-phase output 0 A ≤ IOUT ≤ 8 A, tr = tf = 10 µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase –3% 3% mV
0.1 A ≤ IOUT ≤ 8 A, tr = tf = 1 µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase ±40
3-phase output 0 A ≤ IOUT ≤ 6 A, tr = tf = 10 µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase –3% 3%
0.1 A ≤ IOUT ≤ 6 A, tr = tf = 1 µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase ±40
2-phase output 0 A ≤ IOUT ≤ 4 A, tr = tf = 10 µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase –3% 3%
0.1 A ≤ IOUT ≤ 4 A, tr = tf = 1 µs, PWM mode, COUT = 22 µF/phase, L = 0.47 µH, CPOL = 22 µF/phase ±40
1-phase output 0 A ≤ IOUT ≤ 2 A, tr = tf = 10 µs, PWM mode, COUT = 22 µF, L = 0.47 µH, CPOL = 22 µF –3% 3%
0.1 A ≤ IOUT ≤ 2 A, tr = tf = 1 µs, PWM mode, COUT = 22 µF, L = 0.47 µH, CPOL = 22 µF ±40
TLNSR Transient line response VVIN_Bx stepping 3 V ↔ 3.5 V, tr = tf = 10 µs, IOUT = IOUT(max) ±5 mV
ILIM FWD Forward current limit for each phase (peak for each switching cycle) Programmable range 1.5 5 A
Step size 0.5
Accuracy, VVIN_Bx ≥ 3 V, ILIM ≥ 3 A –5% 7.5% 20%
Accuracy, 2.8 V ≤ VVIN_Bx < 3 V, ILIM ≥ 3. A –20% 7.5% 20%
ILIM NEG Negative current limit per phase (peak for each switching cycle) 1.6 2 2.4 A
RDS(ON) HS FET On-resistance, high-side FET Each phase, between VIN_Bx and SW_Bx pins, I = 1 A 29 65 mΩ
RDS(ON) LS FET On-resistance, low-side FET Each phase, between SW_Bx and PGND_Bx pins, I = 1 A 17 35 mΩ
fSW Switching frequency, PWM mode 1.8 2 2.2 MHz
Current balancing for multiphase outputs Current mismatch between phases, IOUT > 1 A/phase 10%
Start-up time (soft start) From ENx to VOUT = 0.35 V (slew-rate control begins), COUT_TOTAL = 44 µF/phase 200 µs
Output voltage slew-rate(5) SLEW_RATEx[2:0] = 2h, COUT-TOTAL ≤ 80 µF/phase –15% 10 15% mV/µs
SLEW_RATEx[2:0] = 3h, COUT-TOTAL ≤ 130 µF/phase –15% 7.5 15%
SLEW_RATEx[2:0] = 4h, COUT-TOTAL ≤ 250 µF/phase –15% 3.8 15%
SLEW_RATEx[2:0] = 5h, COUT-TOTAL ≤ 500 µF/phase –15% 1.9 15%
SLEW_RATEx[2:0] = 6h, COUT-TOTAL ≤ 500 µF/phase –15% 0.94 15%
SLEW_RATEx[2:0] = 7h, COUT-TOTAL ≤ 500 µF/phase –15% 0.47 15%
IPFM-PWM PFM-to-PWM current threshold(6) 600 mA
IPWM-PFM PWM-to-PFM current threshold(6) 200 mA
IADD Phase adding level (multiphase rails) From 1-phase to 2-phase 1 A
From 2-phase to 3-phase 2
From 3-phase to 4-phase 3
ISHED Phase shedding level (multiphase rails) From 2-phase to 1-phase 0.7 A
From 3-phase to 2-phase 1.5
From 4-phase to 3-phase 2.4
Output pulldown resistance Regulator disabled 160 230 300 Ω
Output voltage monitoring for PGOOD pin Overvoltage monitoring (compared to DC output-voltage level, VVOUT_DC) 39 50 64 mV
Undervoltage monitoring (compared to DC output-voltage level, VVOUT_DC) –53 –40 –29
Debounce time during regulator enable PGOOD_SET_DELAY = 0h 4 10 µs
Debounce time during regulator enable PGOOD_SET_DELAY = 1h 10 11 13 ms
Deglitch time during operation and after voltage change 4 10 µs
Power-good threshold for interrupt BUCKx_PG_INT, difference from final voltage Rising ramp voltage, enable or voltage change –20 –14 –8 mV
Falling ramp voltage, voltage change 8 14 20
Power-good threshold for status bit BUCKx_PG_STAT During operation, status signal is forced to 0h during voltage change –20 –14 –8 mV
EXTERNAL CLOCK AND PLL
Nominal frequency of the external input clock 1 24 MHz
Nominal frequency step size of the external input clock 1 MHz
Required accuracy from nominal frequency of the external input clock –30% 10%
Delay time for missing external clock detection 1.8 µs
Delay and debounce time for external clock detection 20 µs
Clock change delay (internal to external)
delay from valid clock detection to use of external clock		 600 µs
Cycle-to-cycle PLL output clock jitter 300 ps, p-p
PROTECTION FUNCTIONS
Thermal warning Temperature rising, TDIE_WARN_LEVEL = 0h 115 125 135 °C
Temperature rising, TDIE_WARN_LEVEL = 1h 127 137 147
Thermal warning hysteresis 20 °C
Thermal shutdown Temperature rising 140 150 160 °C
Thermal shutdown hysteresis 20 °C
VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V
Voltage falling 5.45 5.73 5.96
VANA overvoltage hysteresis 40 mV
VANAUVLO VANA undervoltage lockout Voltage rising 2.51 2.63 2.75 V
Voltage falling 2.5 2.6 2.7
LOAD CURRENT MEASUREMENT
Current measurement range Output current for maximum code  20.47 A
Resolution LSB 20 mA
Measurement accuracy IOUT > 1 A < 10%
Measurement time PFM mode (automatically changing to PWM mode for the measurement) 45 µs
PWM mode 4
CURRENT CONSUMPTION
Shutdown current consumption From VANA and VIN_Bx pins, NRST = 0 V, VANA = VIN_Bx = 3.7 V 1.4 µA
Standby current consumption From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, regulators disabled 6.7 µA
Active current consumption in PFM mode 4-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled 77 µA
3-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled 71
2-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled 65
1-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled 57
Active current consumption during PWM operation Each phase 17 mA
PLL and clock detector current consumption Additional current consumption when internal RC oscillator, clock detector and PLL are enabled 2 mA
DIGITAL INPUT SIGNALS: NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
VIL Input low level 0.4 V
VIH Input high level 1.2 V
VHYS Hysteresis of Schmitt trigger inputs 10 77 200 mV
ENx pulldown resistance ENx_PD = 1h 500 kΩ
NRST pulldown resistance Always present 650 1150 1700 kΩ
DIGITAL OUTPUT SIGNALS: nINT
VOL Output low level ISOURCE = 2 mA 0.4 V
RP External pullup resistor To VIO supply 10 kΩ
DIGITAL OUTPUT SIGNALS: SDA
VOL Output low level ISOURCE = 10 mA 0.4 V
DIGITAL OUTPUT SIGNALS: PGOOD, GPIO1, GPIO2, GPIO3
VOL Output low level ISOURCE = 2 mA 0.4 V
VOH Output high level, configured to push-pull ISINK = 2 mA VVANA – 0.4 VVANA V
VPU Supply voltage for external pull-up resistor, configured to open-drain VVANA V
RPU External pullup resistor, configured to open-drain 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs over pin voltage range (except NRST) −1 1 µA
(1) All voltage values are with respect to network ground.
(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm.
(3) The output voltage slew-rate setting may limit the maximum output capacitance.
(4) The maximum output current can be limited by the forward current limit ILIM FWD and by the junction temperature. The power dissipation inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown level if the board and ambient temperatures are high.
(5) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The actual set fixed slew rate value for specific part number is listed in corresponding TRM document.
(6) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level.