JAJSF48 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Address: 0x29
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| HALF_DELAY | EN_PG0
_NINT |
PGOOD_SET
_DELAY |
EN_PGFLT
_STAT |
Reserved | PGOOD_
WINDOW |
PGOOD_OD | PGOOD_POL |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | HALF_DELAY | R/W | X | This bit elects the time step for the start-up and shutdown delays.
0h = Start-up and shutdown delays have 0.5-ms or 1-ms time steps, based on the DOUBLE_DELAY bit in the CONFIG register. 1h = Start-up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on the DOUBLE_DELAY bit in the CONFIG register. |
| 6 | EN_PG0_NINT | R/W | X | This bit combines theBUCK0 PGOOD signal with the nINT signal
0h = BUCK0 PGOOD signal not included with the nINT signal 1h = BUCK0 PGOOD signal included with the nINT signal. If the nINT OR the BUCK0 PGOOD signal is low then the nINT signal is low. |
| 5 | PGOOD_SET_DELAY | R/W | X | Debounce time of the output voltage monitoring for the PGOOD signal (only when the PGOOD signal goes valid)
0h = 4-10 µs 1h = 11 ms |
| 4 | EN_PGFLT_STAT | R/W | X | Operation mode for PGOOD signal
0h = Indicates live status of monitored voltage outputs 1h = Indicates status of the PGOOD_FLT register, inactive if at least one of the PGx_FLT bit is inactive |
| 3 | Reserved | R/W | 0h | |
| 2 | PGOOD_WINDOW | R/W | X | Voltage monitoring method for the PGOOD signal
0h = Only undervoltage monitoring 1h = Overvoltage and undervoltage monitoring |
| 1 | PGOOD_OD | R/W | X | PGOOD signal type
0h = Push-pull output (VANA level) 1h = Open-drain output |
| 0 | PGOOD_POL | R/W | X | PGOOD signal polarity
0h = PGOOD signal high when monitored outputs are valid 1h = PGOOD signal low when monitored outputs are valid |