JAJSF48 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Address: 0x2D
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | GPIO3_OD | GPIO2_OD | GPIO1_OD | Reserved | GPIO3_DIR | GPIO2_DIR | GPIO1_DIR |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | Reserved | R | 0h | |
6 | GPIO3_OD | R/W | X | GPIO3 signal type when configured as an output
0h = Push-pull output (VANA level) 1h = Open-drain output |
5 | GPIO2_OD | R/W | X | GPIO2 signal type when configured as an output
0h = Push-pull output (VANA level) 1h = Open-drain output |
4 | GPIO1_OD | R/W | X | GPIO1 signal type when configured as an output
0h = Push-pull output (VANA level) 1h = Open-drain output |
3 | Reserved | R | 0h | |
2 | GPIO3_DIR | R/W | X | GPIO3 signal direction
0h = Input 1h = Output |
1 | GPIO2_DIR | R/W | X | GPIO2 signal direction
0h = Input 1h = Output |
0 | GPIO1_DIR | R/W | X | GPIO1 signal direction
0h = Input 1h = Output |