JAJSF48 March   2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1 Multi-Phase DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Multiphase Operation, Phase Adding, and Phase-Shedding
        3. 8.3.1.3 Transition Between PWM and PFM Modes
        4. 8.3.1.4 Multiphase Switcher Configurations
        5. 8.3.1.5 Buck Converter Load-Current Measurement
        6. 8.3.1.6 Spread-Spectrum Mode
      2. 8.3.2 Sync Clock Functionality
      3. 8.3.3 Power-Up
      4. 8.3.4 Regulator Control
        1. 8.3.4.1 Enabling and Disabling Regulators
        2. 8.3.4.2 Changing Output Voltage
      5. 8.3.5 Enable and Disable Sequences
      6. 8.3.6 Device Reset Scenarios
      7. 8.3.7 Diagnosis and Protection Features
        1. 8.3.7.1 Power-Good Information (PGOOD Pin)
        2. 8.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 8.3.7.2.1 Output Power Limit
          2. 8.3.7.2.2 Thermal Warning
        3. 8.3.7.3 Protection (Regulator Disable)
          1. 8.3.7.3.1 Short-Circuit and Overload Protection
          2. 8.3.7.3.2 Overvoltage Protection
          3. 8.3.7.3.3 Thermal Shutdown
        4. 8.3.7.4 Fault (Power Down)
          1. 8.3.7.4.1 Undervoltage Lockout
      8. 8.3.8 GPIO Signal Operation
      9. 8.3.9 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto-Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1  OTP_REV
        2. 8.6.1.2  BUCK0_CTRL1
        3. 8.6.1.3  BUCK0_CTRL2
        4. 8.6.1.4  BUCK1_CTRL1
        5. 8.6.1.5  BUCK1_CTRL2
        6. 8.6.1.6  BUCK2_CTRL1
        7. 8.6.1.7  BUCK2_CTRL2
        8. 8.6.1.8  BUCK3_CTRL1
        9. 8.6.1.9  BUCK3_CTRL2
        10. 8.6.1.10 BUCK0_VOUT
        11. 8.6.1.11 BUCK0_FLOOR_VOUT
        12. 8.6.1.12 BUCK1_VOUT
        13. 8.6.1.13 BUCK1_FLOOR_VOUT
        14. 8.6.1.14 BUCK2_VOUT
        15. 8.6.1.15 BUCK2_FLOOR_VOUT
        16. 8.6.1.16 BUCK3_VOUT
        17. 8.6.1.17 BUCK3_FLOOR_VOUT
        18. 8.6.1.18 BUCK0_DELAY
        19. 8.6.1.19 BUCK1_DELAY
        20. 8.6.1.20 BUCK2_DELAY
        21. 8.6.1.21 BUCK3_DELAY
        22. 8.6.1.22 GPIO2_DELAY
        23. 8.6.1.23 GPIO3_DELAY
        24. 8.6.1.24 RESET
        25. 8.6.1.25 CONFIG
        26. 8.6.1.26 INT_TOP1
        27. 8.6.1.27 INT_TOP2
        28. 8.6.1.28 INT_BUCK_0_1
        29. 8.6.1.29 INT_BUCK_2_3
        30. 8.6.1.30 TOP_STAT
        31. 8.6.1.31 BUCK_0_1_STAT
        32. 8.6.1.32 BUCK_2_3_STAT
        33. 8.6.1.33 TOP_MASK1
        34. 8.6.1.34 TOP_MASK2
        35. 8.6.1.35 BUCK_0_1_MASK
        36. 8.6.1.36 BUCK_2_3_MASK
        37. 8.6.1.37 SEL_I_LOAD
        38. 8.6.1.38 I_LOAD_2
        39. 8.6.1.39 I_LOAD_1
        40. 8.6.1.40 PGOOD_CTRL1
        41. 8.6.1.41 PGOOD_CTRL2
        42. 8.6.1.42 PGOOD_FLT
        43. 8.6.1.43 PLL_CTRL
        44. 8.6.1.44 PIN_FUNCTION
        45. 8.6.1.45 GPIO_CONFIG
        46. 8.6.1.46 GPIO_IN
        47. 8.6.1.47 GPIO_OUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Inductor Selection
        2. 9.2.1.2 Input Capacitor Selection
        3. 9.2.1.3 Output Capacitor Selection
        4. 9.2.1.4 Snubber Components
        5. 9.2.1.5 Supply Filtering Components
        6. 9.2.1.6 Current Limit vs. Maximum Output Current
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RNF|26
サーマルパッド・メカニカル・データ
発注情報

8.3.7 Diagnosis and Protection Features

The LP8756x-Q1 is capable of providing four levels of protection features:

  • Information of valid regulator output voltage, which sets interrupt or PGOOD signal;
  • Warnings for diagnosis, which set interrupt;
  • Protection events that are disabling the regulators affected; and
  • Faults that are causing the device to shut down.

The LP8756x-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.

When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next start-up.

Table 5. Summary of Interrupt Signals

EVENT RESULT INTERRUPT REGISTER AND BIT INTERRUPT MASK STATUS BIT RECOVERY/INTERRUPT CLEAR
Current limit triggered (20-µs debounce) Interrupt INT_BUCKx = 1
BUCKx_ILIM_INT = 1		 BUCKx_ILIM_MASK BUCKx_ILIM_STAT Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current limit is active.
Short circuit (VVOUT < 0.35 V at 1 ms after enable) or overload (VVOUT decreasing below 0.35 V during operation, 1 ms debounce) Regulator disable and interrupt INT_BUCKx = 1
BUCKx_SC_INT = 1		 N/A N/A Write 1 to BUCKx_SC_INT bit
Thermal warning Interrupt TDIE_WARN = 1 TDIE_WARN_MASK TDIE_WARN_STAT Write 1 to TDIE_WARN bit
Interrupt is not cleared if temperature is above thermal warning level.
Thermal whutdown All regulators disabled and Output GPIOx set to low and interrupt. TDIE_SD = 1 N/A TDIE_SD_STAT Write 1 to TDIE_SD bit
Interrupt is not cleared if temperature is above thermal shutdown level.
VANA overvoltage (VANAOVP) All regulators disabled and Output GPIOx set to low and interrupt. INT_OVP N/A OVP_STAT Write 1 to INT_OVP bit
Interrupt is not cleared if VANA voltage is above VANA OVP level.
Power Good, output voltage reaches the programmed value Interrupt INT_BUCKx = 1
BUCKx_PG_INT = 1		 BUCKx_PG_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit
GPIO Interrupt INT_GPIO GPIO_MASK GPIO_IN register Write 1 to INT_GPIO bit
External clock appears or disappears Interrupt NO_SYNC_CLK(1) SYNC_CLK_MASK SYNC_CLK_STAT Write 1 to NO_SYNC_CLK bit
Load current measurement ready Interrupt I_LOAD_READY = 1 I_LOAD_READY_MASK N/A Write 1 to I_LOAD_READY bit
Start-up (NRST rising edge) Device ready for operation; registers reset to default values and interrupt. RESET_REG = 1 RESET_REG_MASK N/A Write 1 to RESET_REG bit
Glitch on supply voltage and UVLO triggered (VANA falling and rising) Immediate shutdown followed by power up; registers reset to default values and interrupt. RESET_REG = 1 RESET_REG_MASK N/A Write 1 to RESET_REG bit
Software requested reset Immediate shutdown followed by power up; registers reset to default values and interrupt. RESET_REG = 1 RESET_REG_MASK N/A Write 1 to RESET_REG bit
(1) Interrupt is generated during clock detector operation, and in cases where clock is not available when clock detector is enabled.