JAJSG84B January   2016  – June 2018 LP8758-E0

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Buck Information
        1. 7.1.1.1 Operating Modes
        2. 7.1.1.2 Programmability
        3. 7.1.1.3 Features
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Overview
        1. 7.3.1.1 Transition between PWM and PFM Modes
        2. 7.3.1.2 Buck Converter Load Current Measurement
        3. 7.3.1.3 Spread-Spectrum Mode
      2. 7.3.2 Power-Up
      3. 7.3.3 Regulator Control
        1. 7.3.3.1 Enabling and Disabling
        2. 7.3.3.2 Changing Output Voltage
      4. 7.3.4 Device Reset Scenarios
      5. 7.3.5 Diagnosis and Protection Features
        1. 7.3.5.1 Warnings for Diagnosis (Interrupt)
          1. 7.3.5.1.1 Output Current Limit
          2. 7.3.5.1.2 Thermal Warning
        2. 7.3.5.2 Protection (Regulator Disable)
          1. 7.3.5.2.1 Short-Circuit and Overload Protection
          2. 7.3.5.2.2 Thermal Shutdown
        3. 7.3.5.3 Fault (Power Down)
          1. 7.3.5.3.1 Undervoltage Lockout
      6. 7.3.6 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  OTP_REV
        2. 7.6.1.2  BUCK0_CTRL1
        3. 7.6.1.3  BUCK0_CTRL2
        4. 7.6.1.4  BUCK1_CTRL1
        5. 7.6.1.5  BUCK1_CTRL2
        6. 7.6.1.6  BUCK2_CTRL1
        7. 7.6.1.7  BUCK2_CTRL2
        8. 7.6.1.8  BUCK3_CTRL1
        9. 7.6.1.9  BUCK3_CTRL2
        10. 7.6.1.10 BUCK0_VOUT
        11. 7.6.1.11 BUCK0_FLOOR_VOUT
        12. 7.6.1.12 BUCK1_VOUT
        13. 7.6.1.13 BUCK1_FLOOR_VOUT
        14. 7.6.1.14 BUCK2_VOUT
        15. 7.6.1.15 BUCK2_FLOOR_VOUT
        16. 7.6.1.16 BUCK3_VOUT
        17. 7.6.1.17 BUCK3_FLOOR_VOUT
        18. 7.6.1.18 BUCK0_DELAY
        19. 7.6.1.19 BUCK1_DELAY
        20. 7.6.1.20 BUCK2_DELAY
        21. 7.6.1.21 BUCK3_DELAY
        22. 7.6.1.22 RESET
        23. 7.6.1.23 CONFIG
        24. 7.6.1.24 INT_TOP
        25. 7.6.1.25 INT_BUCK_0_1
        26. 7.6.1.26 INT_BUCK_2_3
        27. 7.6.1.27 TOP_STAT
        28. 7.6.1.28 BUCK_0_1_STAT
        29. 7.6.1.29 BUCK_2_3_STAT
        30. 7.6.1.30 TOP_MASK
        31. 7.6.1.31 BUCK_0_1_MASK
        32. 7.6.1.32 BUCK_2_3_MASK
        33. 7.6.1.33 SEL_I_LOAD
        34. 7.6.1.34 I_LOAD_2
        35. 7.6.1.35 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Input Capacitor Selection
          3. 8.2.2.1.3 Output Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V, unless otherwise noted.(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EXTERNAL COMPONENTS
CIN Input filtering capacitance Connected from VIN_Bx to PGND_Bx 1.9 10 µF
COUT Output filtering capacitance, local Capacitance per output voltage rail 10 22 µF
COUT-TOTAL Output capacitance, total (local and remote) Total output capacitance 50 µF
ESRC Input and output capacitor ESR [1-10] MHz 2 10 mΩ
L Inductor Inductance of the inductor 0.47 µH
–30% 30%
DCRL Inductor DCR TDK, VLS252010HBX-R47M 29 mΩ
BUCK REGULATORS
VIN Input voltage range Voltage between VIN_Bx and ground terminals. VANA must be connected to the same supply as VIN_Bx. 2.5 3.7 5.5 V
VOUT Output voltage Programmable voltage range 0.5 1 3.36 V
Step size, 0.5 V ≤ VOUT < 0.73 V 10 mV
Step size, 0.73 V ≤ VOUT < 1.4 V 5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V 20
IOUT Output current Output current, VIN ≤ 3 V 3(3) A
Output current, VIN > 3 V, VOUT ≤ 2 V 4(3)
Output current, VIN > 3 V, VOUT > 2 V 3.5(3)
Dropout voltage VIN – VOUT 0.7 V
DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature Force PWM mode min (–2%,
–20 mV) 		max (2%, 20 mV)
PFM mode, the average output voltage level is increased by max. 20 mV min (–2%,
–20 mV)		 max ( 2%, 20 mV) + 20 mV
Ripple PWM mode, L = 0.47 µH 10 mVp-p
PFM mode, L = 0.47 µH 20
DCLNR DC line regulation IOUT = 1 A ±0.05 %/V
DCLDR DC load regulation in PWM mode IOUT from 0 to IOUT(max) 0.3%
TLDSR Transient load step response IOUT = 0 A to 2 A, TR = TF = 400 ns, PWM mode, COUT = 44 µF, L = 0.47 µH ±55 mV
TLNSR Transient line response VIN stepping 3.3 V ↔ 3.8 V, TR = TF = 10 µs, IOUT = IOUT(max) ±15 mV
ILIM FWD Forward current limit (peak for every switching cycle), per phase Programmable range 2.5 5 A
Step size 0.5
Accuracy, 3 V ≤ VIN ≤ 5.5 V, ILIM FWD = 5 A -5% 7.5% 20%
Accuracy, 2.5 V ≤ VIN ≤ 3 V, ILIM FWD = 5 A -20% 7.5% 20%
ILIM NEG Negative current limit 1.6 2 2.4 A
RDS(ON) HS FET On-resistance, high-side FET Between VIN_Bx and SW_Bx pins (I = 1 A) 40 90 mΩ
RDS(ON) LS FET On-resistance, low-side FET Between SW_Bx and PGND_Bx pins
(I = 1 A)		 33 50 mΩ
Overshoot during start-up Slew-rate = 10 mV/µs < 50 mV
IPFM-PWM PFM-to-PWM switch - current threshold(4) 600 mA
IPWM-PFM PWM-to-PFM switch - current threshold(4) 240 mA
Output pulldown resistance Regulator disabled 150 250 350 Ω
Powergood threshold for interrupt BUCKx_INT(BUCKx_SC_INT), difference from final voltage Rising ramp voltage, enable or voltage change –23 –17 –10 mV
Falling ramp, voltage change 10 17 23
Powergood threshold for status signal BUCKx_STAT(BUCKx_PG_STAT) During operation, status signal is forced to 0 during voltage change –23 –17 –10 mV
PROTECTION FEATURES
Thermal warning Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 0 125 °C
Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 1 105
Hysteresis 15
Thermal shutdown Temperature rising 150 °C
Hysteresis 15
VANAUVLO VANA undervoltage lockout Voltage falling 2.3 2.4 2.5 V
Hysteresis 50 mV
LOAD CURRENT MEASUREMENT
Current measurement range Maximum code 20.46 A
Resolution LSB 20 mA
Measurement accuracy IOUT ≥ 1 A < 10%
CURRENT CONSUMPTION
Shutdown current consumption V(NRST) = 0 V 1 µA
Standby current consumption, converter cores disabled V(NRST) = 1.8 V 6 µA
Active current consumption during PFM operation, one converter core enabled V(NRST) = 1.8 V, IOUT = 0 mA, not switching 55 µA
Active current consumption during PWM operation, per converter core V(NRST) = 1.8 V, IOUT = 0 mA, L = 0.47 µH 14.5 mA
DIGITAL INPUT SIGNALS NRST, ENx, SCL, SDA
VIL Input low level 0.4 V
VIH Input high level 1.2 V
VHYS Hysteresis of Schmitt trigger inputs (SCL, SDA) 10 80 160 mV
ENx pulldown resistance ENx_PD = 1 350 500 720 kΩ
NRST pulldown resistance Always present 800 1200 1700 kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL Output low level ISOURCE = 2 mA, 0.4 V
RP External pullup resistor for nINT To VIO Supply 10 kΩ
ALL DIGITAL INPUTS
ILEAK Input current All logic inputs over pin voltage range −1 1 µA
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.
(3) The maximum output current can be limited by the forward current limit, ILIM FWD. The maximum output current is available with 5-A forward current limit setting.
(4) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the magnitude of inductor's ripple current.