SNOSCX9A March   2015  – November 2015 LPV542

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics 1.8 V
    6. 6.6 Electrical Characteristics 3.3 V
    7. 6.7 Electrical Characteristics 5 V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Rail-To-Rail Input
      2. 7.4.2 Supply Current Changes over Common Mode
      3. 7.4.3 Design Optimization With Rail-To-Rail Input
      4. 7.4.4 Design Optimization for Nanopower Operation
      5. 7.4.5 Common-Mode Rejection
      6. 7.4.6 Output Stage
      7. 7.4.7 Driving Capacitive Load
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: 60 Hz Twin "T" Notch Filter
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The V+ pin should be bypassed to ground with a low ESR capacitor.

The optimum placement is closest to the V+ and ground pins.

Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and ground.

The ground pin should be connected to the PCB ground plane at the pin of the device.

The feedback components should be placed as close to the device as possible to minimize strays.

There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the V- pin. For best performance the DAP should be connected to the exact same potential as the V- pin. Do not use the DAP as the primary V- supply. Floating the DAP pad is not recommended. The DAP and V- pin should be joined directly as shown in the Layout Example.

10.2 Layout Example

LPV542 LPV542_SON_LAYOUT_EXAMPL.png Figure 41. X1SON Layout Example (top view)