JAJSFD1B may   2018  – may 2023 LSF0102-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics (Translating Down): VCCB = 3.3 V
    7. 6.7  Switching Characteristics (Translating Down): VCCB = 2.5 V
    8. 6.8  Switching Characteristics Translating Up): VCCB = 3.3 V
    9. 6.9  Switching Characteristics (Translating Up): VCCB = 2.5 V
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Auto Bidirectional Voltage Translation
      2. 8.3.2 Output Enable
      3. 8.3.3 Device Functional Modes
        1. 8.3.3.1 Up and Down Translation
          1. 8.3.3.1.1 Up Translation
          2. 8.3.3.1.2 Down Translation
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Bidirectional Translation
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
          2. 9.2.1.1.2 Bias Circuitry
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bidirectional Translation
          2. 9.2.1.2.2 Pull-Up Resistor Sizing
          3. 9.2.1.2.3 Application Curve
          4. 9.2.1.2.4 Mixed-Mode Voltage Translation
          5. 9.2.1.2.5 Single Supply Translation
          6. 9.2.1.2.6 Voltage Translation for Vref_B < Vref_A + 0.8 V
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.2 Output Enable

To enable the I/O pins, the EN input should be tied directly to Vref_B during operation and both pins must be pulled up to the HIGH side (VCCB) through a bias resistor (typically 200 kΩ). To ensure the high impedance state during power-up, power-down, or during operation, the EN pin must be LOW. The EN pin should always be tied directly to the Vref_B pin and is recommended to be disabled by an open-drain driver without a pullup resistor. This allows Vref_B to regulate the EN input and bias the channels for proper translation. A filter capacitor on Vref_B is recommended for a stable supply at the device.

GUID-20221012-SS0I-DNWV-CQMH-CMCPD96NMMNG-low.svgFigure 8-1 EN Pin Tied to Vref_B Directly and to VCCB Through a Pull-Up Resistor

The supply voltage of open drain I/O devices can be completely different from the supplies used for the LSF and has no impact on the operation. For additional details on how to use the enable pin, see the Using the Enable Pin with the LSF Family video.

Table 8-1 EN Pin Function Table
INPUT EN(1) PINData Port State
Tied directly to Vref_BAn = Bn
LHi-Z
(1) EN is controlled by Vref_B logic levels.