SLOS018I May   1988  – July 2016 LT1013 , LT1013AM , LT1013D , LT1013M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: LT1013C, ±15 V
    6. 6.6  Electrical Characteristics: LT1013C, 5 V
    7. 6.7  Electrical Characteristics: LT1013D, ±15 V
    8. 6.8  Electrical Characteristics: LT1013D, 5 V
    9. 6.9  Electrical Characteristics: LT1013DI, ±15 V
    10. 6.10 Electrical Characteristics: LT1013DI, 5 V
    11. 6.11 Electrical Characteristics: LT1013M, ±15 V
    12. 6.12 Electrical Characteristics: LT1013M, 5 V
    13. 6.13 Electrical Characteristics: LT1013AM, ±15 V
    14. 6.14 Electrical Characteristics: LT1013AM, 5 V
    15. 6.15 Electrical Characteristics: LT1013DM, ±15 V
    16. 6.16 Electrical Characteristics: LT1013DM, 5 V
    17. 6.17 Operating Characteristics
    18. 6.18 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Resistors
      2. 7.3.2 Output Stage
      3. 7.3.3 Low-Supply Operation
      4. 7.3.4 Output Phase Reversal Protection
        1. 7.3.4.1 Comparator Applications
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Developmental Support
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use quality PCB layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.
    • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.
  • Run the input traces as far away from the supply or output traces as possible to reduce parasitic coupling. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Guidelines.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

10.2 Layout Examples

LT1013 LT1013D LT1013M LT1013AM layout1.gif Figure 29. Operational Amplifier Schematic for Noninverting Configuration
LT1013 LT1013D LT1013M LT1013AM layout_SLOS018.gif Figure 30. Operational Amplifier Board Layout for Noninverting Configuration