JAJSST5A June   2015  – February 2024 LV14540

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Fixed Frequency Peak Current Mode Control
      2. 6.3.2  Slope Compensation
      3. 6.3.3  Pulse Skipping Mode
      4. 6.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 6.3.5  Adjustable Output Voltage
      6. 6.3.6  Enable and Adjustable Undervoltage Lockout
      7. 6.3.7  External Soft Start
      8. 6.3.8  Switching Frequency and Synchronization (RT/SYNC)
      9. 6.3.9  Overcurrent and Short-Circuit Protection
      10. 6.3.10 Overvoltage Protection
      11. 6.3.11 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 CCM Mode
      4. 6.4.4 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Set-Point
        2. 7.2.2.2 Switching Frequency
        3. 7.2.2.3 Output Inductor Selection
        4. 7.2.2.4 Output Capacitor Selection
        5. 7.2.2.5 Schottky Diode Selection
        6. 7.2.2.6 Input Capacitor Selection
        7. 7.2.2.7 Bootstrap Capacitor Selection
        8. 7.2.2.8 Soft-start Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.6 Enable and Adjustable Undervoltage Lockout

The LV14540 is enabled when the VIN pin voltage rises above 3.7 V (typical) and the EN pin voltage exceeds the enable threshold of 1.2 V (typical). The LV14540 is disabled when the VIN pin voltage falls below 3.42 V (typical) or when the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source (typically IEN = 1 μA) that enables operation of the LV14540 when the EN pin is floating.

Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 6-3 to establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power as well as battery power. It can be used for sequencing, making sure of reliable operation, or supply protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.

When EN terminal voltage exceeds 1.2 V, an additional hysteresis current (typically IHYS = 3.6 μA) is sourced out of the EN terminal. When the EN terminal is pulled below 1.2 V, IHYS current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use Equation 2 and Equation 3 to calculate RENT and RENB for desired UVLO hysteresis voltage.

GUID-F6FBEE4D-FDF6-48EF-B301-EBF497B18889-low.gifFigure 6-3 System UVLO by Enable Dividers
Equation 2. GUID-863DB7B8-22C5-4334-AE00-C7B27E1CDED8-low.gif
Equation 3. GUID-0BDF5719-4D2E-4552-8D23-1B52374C3080-low.gif

where VSTART is the desired voltage threshold to enable LV14540, VSTOP is the desired voltage threshold to disable device.